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[S] Change in gem5/gem5[develop]: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fc...

RC
Roger Chang (Gerrit)
Fri, May 12, 2023 12:01 AM

Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70377?usp=email )

Change subject: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu,
fcvt_d_l fcvt_d_lu
......................................................................

arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l
fcvt_d_lu

These instructions use type casting methods to convert integer to
float, so the fflags couldn't trace the event of these. It should
use the function xx_to_f64 to convert from integer to float

Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70377
Reviewed-by: Jason Lowe-Power power.jg@gmail.com
Tested-by: kokoro noreply+kokoro@google.com
Maintainer: Jason Lowe-Power power.jg@gmail.com

M src/arch/riscv/isa/decoder.isa
1 file changed, 12 insertions(+), 4 deletions(-)

Approvals:
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 755be3d..69b3055 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2069,22 +2069,30 @@
0x69: decode CONV_SGN {
0x0: fcvt_d_w({{
RM_REQUIRED;

  •                    Fd = (double)Rs1_sw;
    
  •                    freg_t fd;
    
  •                    fd = freg(i32_to_f64(Rs1_sw));
    
  •                    Fd_bits = fd.v;
                    }}, FloatCvtOp);
                    0x1: fcvt_d_wu({{
                        RM_REQUIRED;
    
  •                    Fd = (double)Rs1_uw;
    
  •                    freg_t fd;
    
  •                    fd = freg(ui32_to_f64(Rs1_uw));
    
  •                    Fd_bits = fd.v;
                    }}, FloatCvtOp);
                    0x2: decode RVTYPE {
                        0x1: fcvt_d_l({{
                            RM_REQUIRED;
    
  •                        Fd = (double)Rs1_sd;
    
  •                        freg_t fd;
    
  •                        fd = freg(i64_to_f64(Rs1_sd));
    
  •                        Fd_bits = fd.v;
                        }}, FloatCvtOp);
                    }
                    0x3: decode RVTYPE {
                        0x1: fcvt_d_lu({{
                            RM_REQUIRED;
    
  •                        Fd = (double)Rs1;
    
  •                        freg_t fd;
    
  •                        fd = freg(ui64_to_f64(Rs1));
    
  •                        Fd_bits = fd.v;
                        }}, FloatCvtOp);
                    }
                }
    

--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72
Gerrit-Change-Number: 70377
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang rogerycchang@google.com
Gerrit-Reviewer: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Hoa Nguyen hoanguyen@ucdavis.edu
Gerrit-Reviewer: Jason Lowe-Power jason@lowepower.com
Gerrit-Reviewer: Jason Lowe-Power power.jg@gmail.com
Gerrit-Reviewer: Roger Chang rogerycchang@google.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com
Gerrit-CC: Yu-hsin Wang yuhsingw@google.com

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70377?usp=email ) Change subject: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fcvt_d_lu ...................................................................... arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fcvt_d_lu These instructions use type casting methods to convert integer to float, so the fflags couldn't trace the event of these. It should use the function xx_to_f64 to convert from integer to float Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70377 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> --- M src/arch/riscv/isa/decoder.isa 1 file changed, 12 insertions(+), 4 deletions(-) Approvals: kokoro: Regressions pass Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 755be3d..69b3055 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -2069,22 +2069,30 @@ 0x69: decode CONV_SGN { 0x0: fcvt_d_w({{ RM_REQUIRED; - Fd = (double)Rs1_sw; + freg_t fd; + fd = freg(i32_to_f64(Rs1_sw)); + Fd_bits = fd.v; }}, FloatCvtOp); 0x1: fcvt_d_wu({{ RM_REQUIRED; - Fd = (double)Rs1_uw; + freg_t fd; + fd = freg(ui32_to_f64(Rs1_uw)); + Fd_bits = fd.v; }}, FloatCvtOp); 0x2: decode RVTYPE { 0x1: fcvt_d_l({{ RM_REQUIRED; - Fd = (double)Rs1_sd; + freg_t fd; + fd = freg(i64_to_f64(Rs1_sd)); + Fd_bits = fd.v; }}, FloatCvtOp); } 0x3: decode RVTYPE { 0x1: fcvt_d_lu({{ RM_REQUIRED; - Fd = (double)Rs1; + freg_t fd; + fd = freg(ui64_to_f64(Rs1)); + Fd_bits = fd.v; }}, FloatCvtOp); } } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70377?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72 Gerrit-Change-Number: 70377 Gerrit-PatchSet: 5 Gerrit-Owner: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Hoa Nguyen <hoanguyen@ucdavis.edu> Gerrit-Reviewer: Jason Lowe-Power <jason@lowepower.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-CC: Yu-hsin Wang <yuhsingw@google.com>