# Increase buffer size to account for more bank resources
  read_buffer_size = 64

  # LPDDR5 is a BL16 or BL32 device
  # With BG mode, BL16 and BL32 are supported
  # Use BL16 for smaller access granularity

  # 4KiB page with 8B mode
  device_rowbuffer_size = "4KiB"

  # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
  tCK = "1.25ns"

  # LPDDR5 is a BL16 or BL32 device
  # With BG mode, BL16 and BL32 are supported
  # Use BL16 for smaller access granularity

  # 4KiB page with 8B mode
  device_rowbuffer_size = "4KiB"

Ayaz Akram has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68257?usp=email ) Change subject: mem: Add a DDR5 memory interface ...................................................................... mem: Add a DDR5 memory interface This change adds a single DDR5 memory inteface. A DDR5 DIMM contains two physical channels. Therefore, two instances of this interface should be used to model a DDR5 DIMM. The configuration includes 3 different speed bins models. The configuration is tested with different types of memory traffic using the traffic generator and shows performance similar to what is observed in existing literature [1]. One of the key features of DDR5 "same bank refresh" is yet not supported in gem5, but is expected to improve the performance of the DDR5 model. [1] Exploration of DDR5 with the Open-Source Simulator DRAMSys. Change-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68257 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/mem/DRAMInterface.py M src/python/SConscript M src/python/gem5/components/memory/__init__.py A src/python/gem5/components/memory/dram_interfaces/ddr5.py M src/python/gem5/components/memory/single_channel.py 5 files changed, 588 insertions(+), 7 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py index 9c041e5..dea62a6 100644 --- a/src/mem/DRAMInterface.py +++ b/src/mem/DRAMInterface.py @@ -41,6 +41,7 @@ from m5.objects.MemCtrl import MemCtrl from m5.objects.MemInterface import * + # Enum for the page policy, either open, open_adaptive, close, or # close_adaptive. class PageManage(Enum): @@ -1179,7 +1180,6 @@ # on HBM gen2 specifications. 4H stack, 8Gb per die and total capacity # of 4GiB. class HBM_2000_4H_1x64(DRAMInterface): - # 64-bit interface for a single pseudo channel device_bus_width = 64 @@ -1256,6 +1256,268 @@ two_cycle_activate = True +# A single DDR5-4400 32bit channel (4x8 configuration) +# A DDR5 DIMM is made up of two (32 bit) channels. +# Following configuration is modeling only a single 32bit channel. +# Timings are based on Micron data sheet: +# https://media-www.micron.com/-/media/client/global/ +# documents/products/data-sheet/dram/ddr5/ddr5_sdram_core.pdf +# Configuration: 4Gbx8 devices (32Gb addressing) +# Maximum bandwidth of DDR5_4400_4x8 (4400 MT/s) can be 17.6GB/s +class DDR5_4400_4x8(DRAMInterface): + # size of a single device + device_size = "512MiB" + + # single channel of 32bit width + # requires 8-bit wide 4 devices + device_bus_width = 8 + + # DDR5 is a BL16 device + burst_length = 16 + + # Each device has a page (row buffer) size of 256B + # Four devices lead to a page size of 1KB + device_rowbuffer_size = "256B" + + # 4Gbx8 configuration + devices_per_rank = 4 + + ranks_per_channel = 1 + + # 4Gbx8 configuration of DDR5 has 8 bank groups, + # 4 banks per bank group and 32 banks in total + bank_groups_per_rank = 8 + banks_per_rank = 32 + + write_buffer_size = 64 + read_buffer_size = 64 + + # For 4400 MT/s + tCK = "0.454ns" + + # 16 beats across an x32 interface translates to 8 clocks @ 2200 MHz + tBURST = "3.632ns" + + # For 4400 MT/s, the number is max(8nCK, 5ns) + tCCD_L = "5ns" + + # page 389 of the data sheet + tRCD = "14.545ns" + tCL = "14.545ns" + # tCWL = tCL - 2(nCK) + tCWL = "13.637ns" + tRP = "14.545ns" + tRAS = "32ns" + + # RRD_S (different bank group) : 8nCK + tRRD = "3.632ns" + + # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page + tRRD_L = "5ns" + + # tFAW for 1KB page is MAX(32nCK, 14.545ns) + tXAW = "14.545ns" + activation_limit = 4 + + # Note: could not find the rank to rank delay + # from the datasheet, but, since we are modeling + # a single rank device, it should not matter. + # Using the DDR4 number as default (i.e. ~2tCK) + tCS = "1ns" + + # tRFC (Normal) for 16Gb device is 295ns + tRFC = "295ns" + + tPPD = "0.908ns" # 2nCK + tWR = "30ns" + + # Rd/Wr turnaround timings + ################################################################### + # Note: gem5 adds tBURST separately while calculting rd--rd/wr or + # wr--wr/rd delays so we can ignore tBURST factor from the following + # equations while calculating the final value of the timing parameter + #################################################################### + # From the datasheet + # (1) tCCD_L_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK + # Therefore, tCCD_L_RTW = + # (14.545 - 13.637) + (2*0.454) - 0.454 + + # ((1.5*0.454)-(0.5*0.454) + (1.5*0.454) = 2.497ns + + # (2) tCCD_S_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # Therefore, tCCD_S_RTW = tCCD_L_RTW = 2.497ns + + # (3) tCCD_L_WTR = + # CWL + WBL/2 + max(16nCK,10ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_L_WTR = 13.637+10 = 23.637ns + + # (4) tCCD_S_WTR = + # CWL + WBL/2 + max(4nCK,2.5ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_S_WTR = 13.637+2.5 = 16.137ns + + tRTW = "2.497ns" + tWTR_L = "23.637ns" + tWTR = "16.137ns" + + # tRTP : max(12nCK, 7.5ns) + tRTP = "7.5ns" + + # <=85C, half for >85C + tREFI = "3.9us" + + # active powerdown and precharge powerdown exit time max(7.5ns, 8nCK) + tXP = "7.5ns" + + # self refresh exit time + # According to the datasheet tXS = tRFC = 295ns (normal Refresh mode) + tXS = "295ns" + + page_policy = "close_adaptive" + + # Power related parameters + # Reference: https://media-www.micron.com/-/media/client/global/ + # documents/products/data-sheet/dram/ddr5/16gb_ddr5_sdram_diereva.pdf + # Using the values for DDR5-4800 + # DDR5 has one voltage domain, so all the + # CurrentVariable2 params should not be used or set to 0 + IDD0 = "122mA" + # Using the value of IDD2P + IDD2P0 = "88mA" + IDD2N = "92mA" + # Using the value of IDD3P + IDD3P0 = "140mA" + IDD3N = "142mA" + IDD4W = "479mA" + IDD4R = "530mA" + # IDD5B - 277, IDD5C -- 135mA, IDD5F -- 262mA in the datasheet + IDD5 = "277mA" + # IDD6N + IDD6 = "102mA" + + VDD = "1.1V" + + +# Maximum bandwidth of DDR5_6400_4x8 (6400 MT/s) can be 25.6GB/s +class DDR5_6400_4x8(DDR5_4400_4x8): + # For 6400 MT/s + tCK = "0.312ns" + + # 16 beats across an x32 interface translates to 8 clocks @ 3200 MHz + tBURST = "2.496ns" + + tRCD = "14.375ns" + tCL = "14.375ns" + # tCWL = tCL - 2(nCK) + tCWL = "13.751ns" + tRP = "14.375ns" + + # RRD_S (different bank group) : 8nCK + tRRD = "2.496ns" + + # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page + tRRD_L = "5ns" + + # tFAW for 1KB page is MAX(32 CK, 10.00ns) + tXAW = "10ns" + + # Rd/Wr turnaround timings + ################################################################### + # Note: gem5 adds tBURST separately while calculting rd--rd/wr or + # wr--wr/rd delays so we can ignore tBURST factor from the following + # equations while calculating the final value of the timing parameter + #################################################################### + # From the datasheet + # (1) tCCD_L_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK + # Therefore, tCCD_L_RTW = + # (14.375 - 13.751) + (2*0.312) - 0.312 + ((1.5*0.312)-(0.5*0.312) + # + (1.5*0.312) = 1.716ns + + # (2) tCCD_S_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.716ns + + # (3) tCCD_L_WTR = + # CWL + WBL/2 + max(16nCK,10ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_L_WTR = 13.751+10 = 23.751ns + + # (4) tCCD_S_WTR = + # CWL + WBL/2 + max(4nCK,2.5ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_S_WTR = 13.751+2.5 = 16.251ns + + tRTW = "1.716ns" + tWTR_L = "23.751ns" + tWTR = "16.251ns" + + +# Maximum bandwidth of DDR5_8400_4x8 (8400 MT/s) can be 33.6GB/s +# Most of the timing parameters for DDR5_8400_4x8 are TBD in +# the datasheet referred above. +# The TBD parameters are extrapolated from the speed bins mentioned above. +class DDR5_8400_4x8(DDR5_4400_4x8): + # For 8400 MT/s + tCK = "0.238ns" + + # 16 beats across an x32 interface translates to 8 clocks @ 4200 MHz + tBURST = "1.904ns" + + tRCD = "14.285ns" + tCL = "14.285ns" + tCWL = "13.809ns" + tRP = "14.285ns" + + # RRD_S (different bank group) : 8nCK + tRRD = "1.904ns" + + # tFAW for 1KB page is MAX(32 CK, 10.00ns) + tXAW = "10ns" + + # Rd/Wr turnaround timings + ################################################################### + # Note: gem5 adds tBURST separately while calculting rd--rd/wr or + # wr--wr/rd delays so we can ignore tBURST factor from the following + # equations while calculating the final value of the timing parameter + #################################################################### + # From the datasheet + # (1) tCCD_L_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK + # Therefore, tCCD_L_RTW = + # (14.285 - 13.809) + (2*0.238) - 0.238 + ((1.5*0.238)-(0.5*0.238) + # + (1.5*0.238) = 1.309ns + + # (2) tCCD_S_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.309ns + + # (3) tCCD_L_WTR = + # CWL + WBL/2 + max(16nCK,10ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_L_WTR =13.809+10 = 23.809ns + + # (4) tCCD_S_WTR = + # CWL + WBL/2 + max(4nCK,2.5ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_S_WTR = 13.809+2.5 = 16.309ns + + tRTW = "1.309ns" + tWTR_L = "23.809ns" + tWTR = "16.309ns" + + # A single LPDDR5 x16 interface (one command/address bus) # for a single x16 channel with default timings based on # initial JEDEC specification @@ -1263,7 +1525,6 @@ # Configuring for 16-bank mode with bank-group architecture # burst of 32, which means bursts can be interleaved class LPDDR5_5500_1x16_BG_BL32(DRAMInterface): - # Increase buffer size to account for more bank resources read_buffer_size = 64 @@ -1390,7 +1651,6 @@ # Starting with 5.5Gbps data rates and 8Gbit die # Configuring for 16-bank mode with bank-group architecture, burst of 16 class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32): - # LPDDR5 is a BL16 or BL32 device # With BG mode, BL16 and BL32 are supported # Use BL16 for smaller access granularity @@ -1412,7 +1672,6 @@ # Starting with 5.5Gbps data rates and 8Gbit die # Configuring for 8-bank mode, burst of 32 class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32): - # 4KiB page with 8B mode device_rowbuffer_size = "4KiB" @@ -1452,7 +1711,6 @@ # Configuring for 16-bank mode with bank-group architecture # burst of 32, which means bursts can be interleaved class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32): - # 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK tCK = "1.25ns" @@ -1497,7 +1755,6 @@ # 6.4Gbps data rates and 8Gbit die # Configuring for 16-bank mode with bank-group architecture, burst of 16 class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32): - # LPDDR5 is a BL16 or BL32 device # With BG mode, BL16 and BL32 are supported # Use BL16 for smaller access granularity @@ -1519,7 +1776,6 @@ # 6.4Gbps data rates and 8Gbit die # Configuring for 8-bank mode, burst of 32 class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32): - # 4KiB page with 8B mode device_rowbuffer_size = "4KiB" diff --git a/src/python/SConscript b/src/python/SConscript index 3b00b34..e261bfa 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -186,6 +186,8 @@ PySource('gem5.components.memory.dram_interfaces', 'gem5/components/memory/dram_interfaces/ddr4.py') PySource('gem5.components.memory.dram_interfaces', + 'gem5/components/memory/dram_interfaces/ddr5.py') +PySource('gem5.components.memory.dram_interfaces', 'gem5/components/memory/dram_interfaces/gddr.py') PySource('gem5.components.memory.dram_interfaces', 'gem5/components/memory/dram_interfaces/hbm.py') diff --git a/src/python/gem5/components/memory/__init__.py b/src/python/gem5/components/memory/__init__.py index 8a7b5ef..546d5d9 100644 --- a/src/python/gem5/components/memory/__init__.py +++ b/src/python/gem5/components/memory/__init__.py @@ -29,6 +29,9 @@ from .single_channel import SingleChannelDDR4_2400 from .single_channel import SingleChannelHBM from .single_channel import SingleChannelLPDDR3_1600 +from .single_channel import DIMM_DDR5_4400 +from .single_channel import DIMM_DDR5_6400 +from .single_channel import DIMM_DDR5_8400 from .multi_channel import DualChannelDDR3_1600 from .multi_channel import DualChannelDDR3_2133 from .multi_channel import DualChannelDDR4_2400 diff --git a/src/python/gem5/components/memory/dram_interfaces/ddr5.py b/src/python/gem5/components/memory/dram_interfaces/ddr5.py new file mode 100644 index 0000000..1ffd7f8 --- /dev/null +++ b/src/python/gem5/components/memory/dram_interfaces/ddr5.py @@ -0,0 +1,292 @@ +# Copyright (c) 2023 The Regents of the University of California +# All Rights Reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +"""Interfaces for DDR5 memories +""" + +from m5.objects import DRAMInterface + + +# A single DDR5-4400 32bit channel (4x8 configuration) +# A DDR5 DIMM is made up of two (32 bit) channels. +# Following configuration is modeling only a single 32bit channel. +# Timings are based on Micron data sheet: +# https://media-www.micron.com/-/media/client/global/ +# documents/products/data-sheet/dram/ddr5/ddr5_sdram_core.pdf +# Configuration: 4Gbx8 devices (32Gb addressing) +# Maximum bandwidth of DDR5_4400_4x8 (4400 MT/s) can be 17.6GB/s +class DDR5_4400_4x8(DRAMInterface): + # size of a single device + device_size = "512MiB" + + # single channel of 32bit width + # requires 8-bit wide 4 devices + device_bus_width = 8 + + # DDR5 is a BL16 device + burst_length = 16 + + # Each device has a page (row buffer) size of 256B + # Four devices lead to a page size of 1KB + device_rowbuffer_size = "256B" + + # 4Gbx8 configuration + devices_per_rank = 4 + + ranks_per_channel = 1 + + # 4Gbx8 configuration of DDR5 has 8 bank groups, + # 4 banks per bank group and 32 banks in total + bank_groups_per_rank = 8 + banks_per_rank = 32 + + write_buffer_size = 64 + read_buffer_size = 64 + + # For 4400 MT/s + tCK = "0.454ns" + + # 16 beats across an x32 interface translates to 8 clocks @ 2200 MHz + tBURST = "3.632ns" + + # For 4400 MT/s, the number is max(8nCK, 5ns) + tCCD_L = "5ns" + + # page 389 of the data sheet + tRCD = "14.545ns" + tCL = "14.545ns" + # tCWL = tCL - 2(nCK) + tCWL = "13.637ns" + tRP = "14.545ns" + tRAS = "32ns" + + # RRD_S (different bank group) : 8nCK + tRRD = "3.632ns" + + # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page + tRRD_L = "5ns" + + # tFAW for 1KB page is MAX(32nCK, 14.545ns) + tXAW = "14.545ns" + activation_limit = 4 + + # Note: could not find the rank to rank delay + # from the datasheet, but, since we are modeling + # a single rank device, it should not matter. + # Using the DDR4 number as default (i.e. ~2tCK) + tCS = "1ns" + + # tRFC (Normal) for 16Gb device is 295ns + tRFC = "295ns" + + tPPD = "0.908ns" # 2nCK + tWR = "30ns" + + # Rd/Wr turnaround timings + ################################################################### + # Note: gem5 adds tBURST separately while calculting rd--rd/wr or + # wr--wr/rd delays so we can ignore tBURST factor from the following + # equations while calculating the final value of the timing parameter + #################################################################### + # From the datasheet + # (1) tCCD_L_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK + # Therefore, tCCD_L_RTW = + # (14.545 - 13.637) + (2*0.454) - 0.454 + + # ((1.5*0.454)-(0.5*0.454) + (1.5*0.454) = 2.497ns + + # (2) tCCD_S_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # Therefore, tCCD_S_RTW = tCCD_L_RTW = 2.497ns + + # (3) tCCD_L_WTR = + # CWL + WBL/2 + max(16nCK,10ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_L_WTR = 13.637+10 = 23.637ns + + # (4) tCCD_S_WTR = + # CWL + WBL/2 + max(4nCK,2.5ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_S_WTR = 13.637+2.5 = 16.137ns + + tRTW = "2.497ns" + tWTR_L = "23.637ns" + tWTR = "16.137ns" + + # tRTP : max(12nCK, 7.5ns) + tRTP = "7.5ns" + + # <=85C, half for >85C + tREFI = "3.9us" + + # active powerdown and precharge powerdown exit time max(7.5ns, 8nCK) + tXP = "7.5ns" + + # self refresh exit time + # According to the datasheet tXS = tRFC = 295ns (normal Refresh mode) + tXS = "295ns" + + page_policy = "close_adaptive" + + # Power related parameters + # Reference: https://media-www.micron.com/-/media/client/global/ + # documents/products/data-sheet/dram/ddr5/16gb_ddr5_sdram_diereva.pdf + # Using the values for DDR5-4800 + # DDR5 has one voltage domain, so all the + # CurrentVariable2 params should not be used or set to 0 + IDD0 = "122mA" + # Using the value of IDD2P + IDD2P0 = "88mA" + IDD2N = "92mA" + # Using the value of IDD3P + IDD3P0 = "140mA" + IDD3N = "142mA" + IDD4W = "479mA" + IDD4R = "530mA" + # IDD5B - 277, IDD5C -- 135mA, IDD5F -- 262mA in the datasheet + IDD5 = "277mA" + # IDD6N + IDD6 = "102mA" + + VDD = "1.1V" + + +# Maximum bandwidth of DDR5_6400_4x8 (6400 MT/s) can be 25.6GB/s +class DDR5_6400_4x8(DDR5_4400_4x8): + # For 6400 MT/s + tCK = "0.312ns" + + # 16 beats across an x32 interface translates to 8 clocks @ 3200 MHz + tBURST = "2.496ns" + + tRCD = "14.375ns" + tCL = "14.375ns" + # tCWL = tCL - 2(nCK) + tCWL = "13.751ns" + tRP = "14.375ns" + + # RRD_S (different bank group) : 8nCK + tRRD = "2.496ns" + + # RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page + tRRD_L = "5ns" + + # tFAW for 1KB page is MAX(32 CK, 10.00ns) + tXAW = "10ns" + + # Rd/Wr turnaround timings + ################################################################### + # Note: gem5 adds tBURST separately while calculting rd--rd/wr or + # wr--wr/rd delays so we can ignore tBURST factor from the following + # equations while calculating the final value of the timing parameter + #################################################################### + # From the datasheet + # (1) tCCD_L_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK + # Therefore, tCCD_L_RTW = + # (14.375 - 13.751) + (2*0.312) - 0.312 + ((1.5*0.312)-(0.5*0.312) + # + (1.5*0.312) = 1.716ns + + # (2) tCCD_S_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.716ns + + # (3) tCCD_L_WTR = + # CWL + WBL/2 + max(16nCK,10ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_L_WTR = 13.751+10 = 23.751ns + + # (4) tCCD_S_WTR = + # CWL + WBL/2 + max(4nCK,2.5ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_S_WTR = 13.751+2.5 = 16.251ns + + tRTW = "1.716ns" + tWTR_L = "23.751ns" + tWTR = "16.251ns" + + +# Maximum bandwidth of DDR5_8400_4x8 (8400 MT/s) can be 33.6GB/s +# Most of the timing parameters for DDR5_8400_4x8 are TBD in +# the datasheet referred above. +# The TBD parameters are extrapolated from the speed bins mentioned above. +class DDR5_8400_4x8(DDR5_4400_4x8): + # For 8400 MT/s + tCK = "0.238ns" + + # 16 beats across an x32 interface translates to 8 clocks @ 4200 MHz + tBURST = "1.904ns" + + tRCD = "14.285ns" + tCL = "14.285ns" + tCWL = "13.809ns" + tRP = "14.285ns" + + # RRD_S (different bank group) : 8nCK + tRRD = "1.904ns" + + # tFAW for 1KB page is MAX(32 CK, 10.00ns) + tXAW = "10ns" + + # Rd/Wr turnaround timings + ################################################################### + # Note: gem5 adds tBURST separately while calculting rd--rd/wr or + # wr--wr/rd delays so we can ignore tBURST factor from the following + # equations while calculating the final value of the timing parameter + #################################################################### + # From the datasheet + # (1) tCCD_L_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK + # Therefore, tCCD_L_RTW = + # (14.285 - 13.809) + (2*0.238) - 0.238 + ((1.5*0.238)-(0.5*0.238) + # + (1.5*0.238) = 1.309ns + + # (2) tCCD_S_RTW = + # CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE + # Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.309ns + + # (3) tCCD_L_WTR = + # CWL + WBL/2 + max(16nCK,10ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_L_WTR =13.809+10 = 23.809ns + + # (4) tCCD_S_WTR = + # CWL + WBL/2 + max(4nCK,2.5ns) + # where WBL/2 = tBURST + # Therefore, + # tCCD_S_WTR = 13.809+2.5 = 16.309ns + + tRTW = "1.309ns" + tWTR_L = "23.809ns" + tWTR = "16.309ns" diff --git a/src/python/gem5/components/memory/single_channel.py b/src/python/gem5/components/memory/single_channel.py index 43aab45..9235bbd 100644 --- a/src/python/gem5/components/memory/single_channel.py +++ b/src/python/gem5/components/memory/single_channel.py @@ -29,6 +29,7 @@ from typing import Optional +from .dram_interfaces.ddr5 import DDR5_4400_4x8, DDR5_6400_4x8, DDR5_8400_4x8 from .dram_interfaces.ddr4 import DDR4_2400_8x8 from .dram_interfaces.hbm import HBM_1000_4H_1x128 from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32 @@ -74,3 +75,30 @@ if not size: size = "256MiB" return ChanneledMemory(HBM_1000_4H_1x128, 1, 64, size=size) + + +def DIMM_DDR5_4400( + size: Optional[str] = None, +) -> AbstractMemorySystem: + """ + A single DIMM of DDR5 has two channels + """ + return ChanneledMemory(DDR5_4400_4x8, 2, 64, size=size) + + +def DIMM_DDR5_6400( + size: Optional[str] = None, +) -> AbstractMemorySystem: + """ + A single DIMM of DDR5 has two channels + """ + return ChanneledMemory(DDR5_6400_4x8, 2, 64, size=size) + + +def DIMM_DDR5_8400( + size: Optional[str] = None, +) -> AbstractMemorySystem: + """ + A single DIMM of DDR5 has two channels + """ + return ChanneledMemory(DDR5_8400_4x8, 2, 64, size=size) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68257?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7 Gerrit-Change-Number: 68257 Gerrit-PatchSet: 4 Gerrit-Owner: Ayaz Akram <yazakram@ucdavis.edu> Gerrit-Reviewer: Ayaz Akram <yazakram@ucdavis.edu> Gerrit-Reviewer: Jason Lowe-Power <jason@lowepower.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Nikos Nikoleris <nikos.nikoleris@arm.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>