Can someone help with this question? zcy <zhongcy93@163.com> 于2023年8月18日周五 15:04写道： > > > > > > > -------- Forwarding messages -------- > From: "chengyong zhong" <zhongcy93@gmail.com> > Date: 2023-01-03 17:51:16 > To: gem5-users@gem5.org,zhongcy93 <zhongcy93@163.com> > Subject: skidBuffer in O3CPU pipeline > There are multiple skidBuffer instance in O3CPU pipeline, the skidBuffers > are used to store instruction when current stage is blocked, and 'consume' > the instruction from skidBuffer when current stage unblocked. My question > is: > 1. Why the skidBuffer is introduced by Gem5, are there any real processor > which use skidbuffer in its pipeline? > 2. As far as I know, the whole previous pipeline blocked after some events > occurs, e.g. a branch predict error detected in execute stage. But after > skidBuffer was introduced, the fetch stage will continue fetch instructions > at the cycle after block. >

Hi Chengyong, There are a few links related to skidBuffer that you can check out: - https://sc19.supercomputing.org/proceedings/workshops/workshop_files/ws_pmbss111s2-file1.pdf [image: Screenshot 2023-08-20 at 12.34.46 PM.png] - https://www.mail-archive.com/gem5-users@gem5.org/msg12282.html - Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors, IEEE CAL. Hope it helps. Jiayi On Fri, Aug 18, 2023 at 3:08 PM chengyong zhong via gem5-users < gem5-users@gem5.org> wrote: > Can someone help with this question? > > zcy <zhongcy93@163.com> 于2023年8月18日周五 15:04写道： > >> >> >> >> >> >> >> -------- Forwarding messages -------- >> From: "chengyong zhong" <zhongcy93@gmail.com> >> Date: 2023-01-03 17:51:16 >> To: gem5-users@gem5.org,zhongcy93 <zhongcy93@163.com> >> Subject: skidBuffer in O3CPU pipeline >> There are multiple skidBuffer instance in O3CPU pipeline, the skidBuffers >> are used to store instruction when current stage is blocked, and 'consume' >> the instruction from skidBuffer when current stage unblocked. My question >> is: >> 1. Why the skidBuffer is introduced by Gem5, are there any real processor >> which use skidbuffer in its pipeline? >> 2. As far as I know, the whole previous pipeline blocked after some >> events occurs, e.g. a branch predict error detected in execute stage. But >> after skidBuffer was introduced, the fetch stage will continue fetch >> instructions at the cycle after block. >> > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-leave@gem5.org >

Hi Jiayi, Thanks for your reply, the scenario which described in the paper have confused me, too. On the other hand, do you know any existed core which has a "buffer" between pipeline? Cheers, Chengyong Jiayi Huang <jyhuang91@gmail.com> 于2023年8月20日周日 12:38写道： > Hi Chengyong, > > There are a few links related to skidBuffer that you can check out: > - > https://sc19.supercomputing.org/proceedings/workshops/workshop_files/ws_pmbss111s2-file1.pdf > [image: Screenshot 2023-08-20 at 12.34.46 PM.png] > - https://www.mail-archive.com/gem5-users@gem5.org/msg12282.html > - Enhanced Dependence Graph Model for Critical Path Analysis on Modern > Out-of-Order Processors, IEEE CAL. > > Hope it helps. > Jiayi > > On Fri, Aug 18, 2023 at 3:08 PM chengyong zhong via gem5-users < > gem5-users@gem5.org> wrote: > >> Can someone help with this question? >> >> zcy <zhongcy93@163.com> 于2023年8月18日周五 15:04写道： >> >>> >>> >>> >>> >>> >>> >>> -------- Forwarding messages -------- >>> From: "chengyong zhong" <zhongcy93@gmail.com> >>> Date: 2023-01-03 17:51:16 >>> To: gem5-users@gem5.org,zhongcy93 <zhongcy93@163.com> >>> Subject: skidBuffer in O3CPU pipeline >>> There are multiple skidBuffer instance in O3CPU pipeline, the >>> skidBuffers are used to store instruction when current stage is blocked, >>> and 'consume' the instruction from skidBuffer when current stage unblocked. >>> My question is: >>> 1. Why the skidBuffer is introduced by Gem5, are there any real >>> processor which use skidbuffer in its pipeline? >>> 2. As far as I know, the whole previous pipeline blocked after some >>> events occurs, e.g. a branch predict error detected in execute stage. But >>> after skidBuffer was introduced, the fetch stage will continue fetch >>> instructions at the cycle after block. >>> >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-leave@gem5.org >> >

I just took a look at the RISC-V BOOM, it has the fetch buffer and issue queues. (It may not be necessary to have deep buffers between every two neighboring pipeline stages, but I am not quite sure about it.) And I believe that some other cores such as Alpha 21264 and SPARC T4 have similar structures to accommodate the different rates of different pipeline stages, especially the frontend and the backend. Regarding the paper, I think the point is that the buffer or queues should be used properly and not always propagate stalls of later stages to the earlier stages if there are free buffer entries in between. I hope this helps. But I am not an expert in the core microarchitecture. So my understanding may be wrong ;) Best, Jiayi On Sun, Aug 20, 2023 at 4:35 PM chengyong zhong <zhongcy93@gmail.com> wrote: > Hi Jiayi, > Thanks for your reply, the scenario which described in the paper have > confused me, too. > On the other hand, do you know any existed core which has a "buffer" > between pipeline? > > Cheers, > Chengyong > > Jiayi Huang <jyhuang91@gmail.com> 于2023年8月20日周日 12:38写道： > >> Hi Chengyong, >> >> There are a few links related to skidBuffer that you can check out: >> - >> https://sc19.supercomputing.org/proceedings/workshops/workshop_files/ws_pmbss111s2-file1.pdf >> [image: Screenshot 2023-08-20 at 12.34.46 PM.png] >> - https://www.mail-archive.com/gem5-users@gem5.org/msg12282.html >> - Enhanced Dependence Graph Model for Critical Path Analysis on Modern >> Out-of-Order Processors, IEEE CAL. >> >> Hope it helps. >> Jiayi >> >> On Fri, Aug 18, 2023 at 3:08 PM chengyong zhong via gem5-users < >> gem5-users@gem5.org> wrote: >> >>> Can someone help with this question? >>> >>> zcy <zhongcy93@163.com> 于2023年8月18日周五 15:04写道： >>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> -------- Forwarding messages -------- >>>> From: "chengyong zhong" <zhongcy93@gmail.com> >>>> Date: 2023-01-03 17:51:16 >>>> To: gem5-users@gem5.org,zhongcy93 <zhongcy93@163.com> >>>> Subject: skidBuffer in O3CPU pipeline >>>> There are multiple skidBuffer instance in O3CPU pipeline, the >>>> skidBuffers are used to store instruction when current stage is blocked, >>>> and 'consume' the instruction from skidBuffer when current stage unblocked. >>>> My question is: >>>> 1. Why the skidBuffer is introduced by Gem5, are there any real >>>> processor which use skidbuffer in its pipeline? >>>> 2. As far as I know, the whole previous pipeline blocked after some >>>> events occurs, e.g. a branch predict error detected in execute stage. But >>>> after skidBuffer was introduced, the fetch stage will continue fetch >>>> instructions at the cycle after block. >>>> >>> _______________________________________________ >>> gem5-users mailing list -- gem5-users@gem5.org >>> To unsubscribe send an email to gem5-users-leave@gem5.org >>> >>

Thanks for the feedback! In my opinion, Gem5 has also implemented the the fetch buffer and IQ, which is corresponding to common microarchitecture, but it seems that skidbuffer is just a "software component" and doesn't map to any hardware components. I got the idea from the paper, thanks very much. Cheers, Chengyong Jiayi Huang <jyhuang91@gmail.com> 于2023年8月21日周一 00:01写道： > I just took a look at the RISC-V BOOM, it has the fetch buffer and issue > queues. (It may not be necessary to have deep buffers between every two > neighboring pipeline stages, but I am not quite sure about it.) And I > believe that some other cores such as Alpha 21264 and SPARC T4 have > similar structures to accommodate the different rates of different pipeline > stages, especially the frontend and the backend. > > Regarding the paper, I think the point is that the buffer or queues should > be used properly and not always propagate stalls of later stages to the > earlier stages if there are free buffer entries in between. > > I hope this helps. But I am not an expert in the core microarchitecture. > So my understanding may be wrong ;) > > Best, > Jiayi > > On Sun, Aug 20, 2023 at 4:35 PM chengyong zhong <zhongcy93@gmail.com> > wrote: > >> Hi Jiayi, >> Thanks for your reply, the scenario which described in the paper have >> confused me, too. >> On the other hand, do you know any existed core which has a "buffer" >> between pipeline? >> >> Cheers, >> Chengyong >> >> Jiayi Huang <jyhuang91@gmail.com> 于2023年8月20日周日 12:38写道： >> >>> Hi Chengyong, >>> >>> There are a few links related to skidBuffer that you can check out: >>> - >>> https://sc19.supercomputing.org/proceedings/workshops/workshop_files/ws_pmbss111s2-file1.pdf >>> [image: Screenshot 2023-08-20 at 12.34.46 PM.png] >>> - https://www.mail-archive.com/gem5-users@gem5.org/msg12282.html >>> - Enhanced Dependence Graph Model for Critical Path Analysis on Modern >>> Out-of-Order Processors, IEEE CAL. >>> >>> Hope it helps. >>> Jiayi >>> >>> On Fri, Aug 18, 2023 at 3:08 PM chengyong zhong via gem5-users < >>> gem5-users@gem5.org> wrote: >>> >>>> Can someone help with this question? >>>> >>>> zcy <zhongcy93@163.com> 于2023年8月18日周五 15:04写道： >>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> -------- Forwarding messages -------- >>>>> From: "chengyong zhong" <zhongcy93@gmail.com> >>>>> Date: 2023-01-03 17:51:16 >>>>> To: gem5-users@gem5.org,zhongcy93 <zhongcy93@163.com> >>>>> Subject: skidBuffer in O3CPU pipeline >>>>> There are multiple skidBuffer instance in O3CPU pipeline, the >>>>> skidBuffers are used to store instruction when current stage is blocked, >>>>> and 'consume' the instruction from skidBuffer when current stage unblocked. >>>>> My question is: >>>>> 1. Why the skidBuffer is introduced by Gem5, are there any real >>>>> processor which use skidbuffer in its pipeline? >>>>> 2. As far as I know, the whole previous pipeline blocked after some >>>>> events occurs, e.g. a branch predict error detected in execute stage. But >>>>> after skidBuffer was introduced, the fetch stage will continue fetch >>>>> instructions at the cycle after block. >>>>> >>>> _______________________________________________ >>>> gem5-users mailing list -- gem5-users@gem5.org >>>> To unsubscribe send an email to gem5-users-leave@gem5.org >>>> >>>