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[M] Change in gem5/gem5[develop]: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.

Bobby Bruce (Gerrit)

Thu, May 25, 2023 9:36 PM

Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email )

(

7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT
insts.
......................................................................

arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.

Re-factored the Arm instruction decoder to add placeholders for the
SVE Integer mixed-sign DOT product instructions. This has involved
moving some existing decode helper functions.

Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218
Reviewed-by: Richard Cooper richard.cooper@arm.com
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70731
Reviewed-by: Andreas Sandberg andreas.sandberg@arm.com
Maintainer: Andreas Sandberg andreas.sandberg@arm.com
Tested-by: kokoro noreply+kokoro@google.com

M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
2 files changed, 133 insertions(+), 29 deletions(-)

Approvals:
kokoro: Regressions pass
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved

diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 4a44bab..0d12a22 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2241,7 +2241,7 @@
}

  StaticInstPtr

decodeSveMultiplyAddUnpred(ExtMachInst machInst)

decodeSveIntegerDotProductUnpred(ExtMachInst machInst)
{
RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
@@ -2273,10 +2273,10 @@
}
```
 return new Unknown64(machInst);
```

} // decodeSveMultiplyAddUnpred

} // decodeSveIntegerDotProductUnpred

StaticInstPtr

decodeSveMultiplyIndexed(ExtMachInst machInst)

decodeSveIntegerDotProductIndexed(ExtMachInst machInst)
{
RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
@@ -2310,7 +2310,59 @@
}
}
return new Unknown64(machInst);

} // decodeSveMultiplyIndexed

} // decodeSveIntegerDotProductIndexed
StaticInstPtr
decodeSveMixedSignDotProduct(ExtMachInst machInst)
{

   uint8_t size = (uint8_t) bits(machInst, 23, 22);

```
   if (size != 0b10) {
```
```
       return new Unknown64(machInst);
```
```
   }
```

   RegIndex zda M5_VAR_USED = (RegIndex)

                                     (uint8_t) bits(machInst, 4, 0);

   RegIndex zn M5_VAR_USED = (RegIndex)

                                     (uint8_t) bits(machInst, 9, 5);

   RegIndex zm M5_VAR_USED = (RegIndex)

                                     (uint8_t) bits(machInst, 20, 16);

```
   // Placeholder for SveUsdotv
```

   //return SveUsdotv<int32_t, uint8_t, int8_t>(machInst, zda, zn,

zm);

```
   return new Unknown64(machInst);
```
} // decodeSveMixedSignDotProduct
StaticInstPtr
decodeSveMixedSignDotProductIndexed(ExtMachInst machInst)
{

   uint8_t size = (uint8_t) bits(machInst, 23, 22);

```
   if (size != 0b10) {
```
```
       return new Unknown64(machInst);
```
```
   }
```

   RegIndex zda M5_VAR_USED = (RegIndex)

                                     (uint8_t) bits(machInst, 4, 0);

   RegIndex zn M5_VAR_USED = (RegIndex)

                                     (uint8_t) bits(machInst, 9, 5);

   RegIndex zm M5_VAR_USED = (RegIndex)

                                     (uint8_t) bits(machInst, 18, 16);

   uint8_t i2 M5_VAR_USED = (uint8_t) bits(machInst, 20, 19);

   uint8_t usig = (uint8_t) bits(machInst, 10);

```
   if (usig) {
```
```
       // Placeholder for SveSudoti
```

       //return SveSudoti<int32_t, int8_t, uint8_t>

       //                         (machInst, zda, zn, zm, i2);

```
       return new Unknown64(machInst);
```
```
   } else {
```
```
       // Placeholder for SveUsdoti
```

       //return SveUsdoti<int32_t, uint8_t, int8_t>

       //                         (machInst, zda, zn, zm, i2);

```
       return new Unknown64(machInst);
```
```
   }
```
} // decodeSveMixedSignDotProductIndexed

StaticInstPtr
decodeSve2ArithCarry(ExtMachInst machInst)
@@ -3851,6 +3903,43 @@
return new Unknown64(machInst);
} // decodeSveMisc
StaticInstPtr
decodeSveIntegerMulAddUnpred(ExtMachInst machInst)
{

   uint8_t op1 = (uint8_t) bits(machInst, 13, 11);

```
   if (bits(machInst, 14) == 0b0) {
```
```
       if (op1 == 0b000) {
```

           return decodeSveIntegerDotProductUnpred(machInst);

```
       } else {
```

           return new Unknown64(machInst);

```
       }
```
```
   } else {
```
```
       if (op1 == 0b111 &&
```

           bits(machInst, 10) == 0b0) {

           return decodeSveMixedSignDotProduct(machInst);

```
       } else {
```

           return new Unknown64(machInst);

```
       }
```
```
   }
```
}
StaticInstPtr
decodeSveMultiplyIndexed(ExtMachInst machInst)
{

   if (bits(machInst, 15, 13) == 0b000) {

       switch (bits(machInst, 12, 11)) {

```
         case 0b00:
```

           return decodeSveIntegerDotProductIndexed(machInst);

```
         case 0b11:
```

           return decodeSveMixedSignDotProductIndexed(machInst);

```
         default:
```

           return new Unknown64(machInst);

```
       }
```
```
   } else {
```
```
       return new Unknown64(machInst);
```
```
   }
```
```
   return new Unknown64(machInst);
```
}

} // namespace Aarch64
}};
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa
b/src/arch/arm/isa/formats/sve_top_level.isa
index 20a15a2..cb390eb 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -72,8 +72,10 @@
StaticInstPtr decodeSveClamp(ExtMachInst machInst);
StaticInstPtr decodeSve2Accum(ExtMachInst machInst);

StaticInstPtr decodeSveMultiplyAddUnpred(ExtMachInst machInst);
StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst);

StaticInstPtr decodeSveIntegerDotProductUnpred(ExtMachInst machInst);
StaticInstPtr decodeSveIntegerDotProductIndexed(ExtMachInst machInst);
StaticInstPtr decodeSveMixedSignDotProduct(ExtMachInst machInst);
StaticInstPtr decodeSveMixedSignDotProductIndexed(ExtMachInst
machInst);

StaticInstPtr decodeSveFpFastReduc(ExtMachInst machInst);
StaticInstPtr decodeSveFpUnaryUnpred(ExtMachInst machInst);
@@ -97,6 +99,8 @@
StaticInstPtr decodeSveMemStore(ExtMachInst machInst);

StaticInstPtr decodeSveMisc(ExtMachInst machInst);
StaticInstPtr decodeSveIntegerMulAddUnpred(ExtMachInst machInst);
StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst);
}
}};

@@ -108,10 +112,33 @@
decodeSveInt(ExtMachInst machInst)
{
if (bits(machInst, 31, 29) == 0b010) {

       if (bits(machInst, 24) == 0b1 &&

           bits(machInst, 21) == 0b0 &&

           bits(machInst, 15, 14)==0b10) {

           return decodeSveMisc(machInst);

       uint8_t op1 = bits(machInst, 24, 23);

       uint8_t op2 = bits(machInst, 15, 14);

```
       switch (op1) {
```
```
         case 0b00:
```
```
         case 0b01:
```

             if (bits(machInst, 21) == 0b0) {

                 if (bits(machInst, 15) == 0b0) {

                     return decodeSveIntegerMulAddUnpred(machInst);

```
                 } else {
```

                     return new Unknown64(machInst);

```
                 }
```
```
             } else {
```

                 return decodeSveMultiplyIndexed(machInst);

```
             }
```
```
             break;
```
```
         case 0b10:
```
```
         case 0b11:
```

             if (bits(machInst, 21) == 0b0 && op2 == 0b10) {

                 return decodeSveMisc(machInst);

             } else if (bits(machInst, 21) == 0b0 && op2 == 0b11) {

                 return decodeSve2Accum(machInst);

```
             } else {
```

                 return new Unknown64(machInst);

```
             }
```
```
             break;
```
```
         default:
```

             return new Unknown64(machInst);
        }
    }

@@ -131,11 +158,10 @@
bits(machInst, 13);
switch (b_15_13) {
case 0x0:

                   if (bits(machInst, 30)) {

                       return decodeSveMultiplyAddUnpred(machInst);

```
                   } else {
```

                   if (!bits(machInst, 30)) {
                        return decodeSveIntArithBinPred(machInst);
                    }

                   break;
                  case 0x1:
                    return decodeSveIntReduc(machInst);
                  case 0x2:

@@ -156,12 +182,11 @@
if (b_13) {
return decodeSveIntLogUnpred(machInst);
} else {

                   if (bits(machInst, 30)) {

                       return decodeSveMultiplyIndexed(machInst);

```
                   } else {
```

                   if (!bits(machInst, 30)) {
                        return decodeSveIntArithUnpred(machInst);
                    }
                }

               break;
              case 0x1:
                if (b_13) {
                    return new Unknown64(machInst);

@@ -187,22 +212,12 @@
}
case 0x2:
{

         if (bits(machInst, 30) == 0) {

```
             if (bits(machInst, 20)) {
```

                 return decodeSveIntWideImmPred(machInst);

```
           if (bits(machInst, 20)) {
```

               return decodeSveIntWideImmPred(machInst);
            } else {
                return decodeSveLogMaskImm(machInst);
            }

```
         } else {
```

           uint8_t b_15_14 = bits(machInst, 15, 14);

```
           switch (b_15_14) {
```
```
             case 3:
```

               return decodeSve2Accum(machInst);

```
             default :
```
```
               break;
```
```
           }
```
```
         }
```
```
         break;
```

           break;
        }
      case 0x3:
        {

--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings?usp=email

Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218
Gerrit-Change-Number: 70731
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini giacomo.travaglini@arm.com
Gerrit-Reviewer: Andreas Sandberg andreas.sandberg@arm.com
Gerrit-Reviewer: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Jason Lowe-Power power.jg@gmail.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com
Gerrit-CC: Richard Cooper richard.cooper@arm.com

Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts. ...................................................................... arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts. Re-factored the Arm instruction decoder to add placeholders for the SVE Integer mixed-sign DOT product instructions. This has involved moving some existing decode helper functions. Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218 Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70731 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/formats/sve_top_level.isa 2 files changed, 133 insertions(+), 29 deletions(-) Approvals: kokoro: Regressions pass Andreas Sandberg: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index 4a44bab..0d12a22 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -2241,7 +2241,7 @@ } StaticInstPtr - decodeSveMultiplyAddUnpred(ExtMachInst machInst) + decodeSveIntegerDotProductUnpred(ExtMachInst machInst) { RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0); RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5); @@ -2273,10 +2273,10 @@ } return new Unknown64(machInst); - } // decodeSveMultiplyAddUnpred + } // decodeSveIntegerDotProductUnpred StaticInstPtr - decodeSveMultiplyIndexed(ExtMachInst machInst) + decodeSveIntegerDotProductIndexed(ExtMachInst machInst) { RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0); RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5); @@ -2310,7 +2310,59 @@ } } return new Unknown64(machInst); - } // decodeSveMultiplyIndexed + } // decodeSveIntegerDotProductIndexed + + StaticInstPtr + decodeSveMixedSignDotProduct(ExtMachInst machInst) + { + uint8_t size = (uint8_t) bits(machInst, 23, 22); + if (size != 0b10) { + return new Unknown64(machInst); + } + + RegIndex zda M5_VAR_USED = (RegIndex) + (uint8_t) bits(machInst, 4, 0); + RegIndex zn M5_VAR_USED = (RegIndex) + (uint8_t) bits(machInst, 9, 5); + RegIndex zm M5_VAR_USED = (RegIndex) + (uint8_t) bits(machInst, 20, 16); + + // Placeholder for SveUsdotv + //return SveUsdotv<int32_t, uint8_t, int8_t>(machInst, zda, zn, zm); + return new Unknown64(machInst); + } // decodeSveMixedSignDotProduct + + StaticInstPtr + decodeSveMixedSignDotProductIndexed(ExtMachInst machInst) + { + uint8_t size = (uint8_t) bits(machInst, 23, 22); + if (size != 0b10) { + return new Unknown64(machInst); + } + + RegIndex zda M5_VAR_USED = (RegIndex) + (uint8_t) bits(machInst, 4, 0); + RegIndex zn M5_VAR_USED = (RegIndex) + (uint8_t) bits(machInst, 9, 5); + RegIndex zm M5_VAR_USED = (RegIndex) + (uint8_t) bits(machInst, 18, 16); + uint8_t i2 M5_VAR_USED = (uint8_t) bits(machInst, 20, 19); + + uint8_t usig = (uint8_t) bits(machInst, 10); + + if (usig) { + // Placeholder for SveSudoti + //return SveSudoti<int32_t, int8_t, uint8_t> + // (machInst, zda, zn, zm, i2); + return new Unknown64(machInst); + } else { + // Placeholder for SveUsdoti + //return SveUsdoti<int32_t, uint8_t, int8_t> + // (machInst, zda, zn, zm, i2); + return new Unknown64(machInst); + } + + } // decodeSveMixedSignDotProductIndexed StaticInstPtr decodeSve2ArithCarry(ExtMachInst machInst) @@ -3851,6 +3903,43 @@ return new Unknown64(machInst); } // decodeSveMisc + StaticInstPtr + decodeSveIntegerMulAddUnpred(ExtMachInst machInst) + { + uint8_t op1 = (uint8_t) bits(machInst, 13, 11); + if (bits(machInst, 14) == 0b0) { + if (op1 == 0b000) { + return decodeSveIntegerDotProductUnpred(machInst); + } else { + return new Unknown64(machInst); + } + } else { + if (op1 == 0b111 && + bits(machInst, 10) == 0b0) { + return decodeSveMixedSignDotProduct(machInst); + } else { + return new Unknown64(machInst); + } + } + } + + StaticInstPtr + decodeSveMultiplyIndexed(ExtMachInst machInst) + { + if (bits(machInst, 15, 13) == 0b000) { + switch (bits(machInst, 12, 11)) { + case 0b00: + return decodeSveIntegerDotProductIndexed(machInst); + case 0b11: + return decodeSveMixedSignDotProductIndexed(machInst); + default: + return new Unknown64(machInst); + } + } else { + return new Unknown64(machInst); + } + return new Unknown64(machInst); + } } // namespace Aarch64 }}; diff --git a/src/arch/arm/isa/formats/sve_top_level.isa b/src/arch/arm/isa/formats/sve_top_level.isa index 20a15a2..cb390eb 100644 --- a/src/arch/arm/isa/formats/sve_top_level.isa +++ b/src/arch/arm/isa/formats/sve_top_level.isa @@ -72,8 +72,10 @@ StaticInstPtr decodeSveClamp(ExtMachInst machInst); StaticInstPtr decodeSve2Accum(ExtMachInst machInst); - StaticInstPtr decodeSveMultiplyAddUnpred(ExtMachInst machInst); - StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst); + StaticInstPtr decodeSveIntegerDotProductUnpred(ExtMachInst machInst); + StaticInstPtr decodeSveIntegerDotProductIndexed(ExtMachInst machInst); + StaticInstPtr decodeSveMixedSignDotProduct(ExtMachInst machInst); + StaticInstPtr decodeSveMixedSignDotProductIndexed(ExtMachInst machInst); StaticInstPtr decodeSveFpFastReduc(ExtMachInst machInst); StaticInstPtr decodeSveFpUnaryUnpred(ExtMachInst machInst); @@ -97,6 +99,8 @@ StaticInstPtr decodeSveMemStore(ExtMachInst machInst); StaticInstPtr decodeSveMisc(ExtMachInst machInst); + StaticInstPtr decodeSveIntegerMulAddUnpred(ExtMachInst machInst); + StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst); } }}; @@ -108,10 +112,33 @@ decodeSveInt(ExtMachInst machInst) { if (bits(machInst, 31, 29) == 0b010) { - if (bits(machInst, 24) == 0b1 && - bits(machInst, 21) == 0b0 && - bits(machInst, 15, 14)==0b10) { - return decodeSveMisc(machInst); + uint8_t op1 = bits(machInst, 24, 23); + uint8_t op2 = bits(machInst, 15, 14); + switch (op1) { + case 0b00: + case 0b01: + if (bits(machInst, 21) == 0b0) { + if (bits(machInst, 15) == 0b0) { + return decodeSveIntegerMulAddUnpred(machInst); + } else { + return new Unknown64(machInst); + } + } else { + return decodeSveMultiplyIndexed(machInst); + } + break; + case 0b10: + case 0b11: + if (bits(machInst, 21) == 0b0 && op2 == 0b10) { + return decodeSveMisc(machInst); + } else if (bits(machInst, 21) == 0b0 && op2 == 0b11) { + return decodeSve2Accum(machInst); + } else { + return new Unknown64(machInst); + } + break; + default: + return new Unknown64(machInst); } } @@ -131,11 +158,10 @@ bits(machInst, 13); switch (b_15_13) { case 0x0: - if (bits(machInst, 30)) { - return decodeSveMultiplyAddUnpred(machInst); - } else { + if (!bits(machInst, 30)) { return decodeSveIntArithBinPred(machInst); } + break; case 0x1: return decodeSveIntReduc(machInst); case 0x2: @@ -156,12 +182,11 @@ if (b_13) { return decodeSveIntLogUnpred(machInst); } else { - if (bits(machInst, 30)) { - return decodeSveMultiplyIndexed(machInst); - } else { + if (!bits(machInst, 30)) { return decodeSveIntArithUnpred(machInst); } } + break; case 0x1: if (b_13) { return new Unknown64(machInst); @@ -187,22 +212,12 @@ } case 0x2: { - if (bits(machInst, 30) == 0) { - if (bits(machInst, 20)) { - return decodeSveIntWideImmPred(machInst); + if (bits(machInst, 20)) { + return decodeSveIntWideImmPred(machInst); } else { return decodeSveLogMaskImm(machInst); } - } else { - uint8_t b_15_14 = bits(machInst, 15, 14); - switch (b_15_14) { - case 3: - return decodeSve2Accum(machInst); - default : - break; - } - } - break; + break; } case 0x3: { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218 Gerrit-Change-Number: 70731 Gerrit-PatchSet: 9 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Andreas Sandberg <andreas.sandberg@arm.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-CC: Richard Cooper <richard.cooper@arm.com>