Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Rename AdvSIMD instruction pool ...................................................................... arch-arm: Rename AdvSIMD instruction pool The decoding function was wrongly named decodeNeon3SameExtra, referring to the "AdvSIMD three same Extra" instruction pool This might be an old name as I can only find the "AdvSIMD *scalar* three same Extra" in the Arm arm. The encoding space reserved to the pool bears the "Advanced SIMD three-register extension" name; we therefore rename the function to decodeNeon3RegExtension Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70724 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> --- M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/neon64.isa 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: kokoro: Regressions pass Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 9ad2de2..47d509e 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -2461,7 +2461,7 @@ return new Unknown64(machInst); } } else if (bits(machInst, 15) == 1) { - return decodeNeon3SameExtra<DecoderFeatures>(machInst); + return decodeNeon3RegExtension<DecoderFeatures>(machInst); } else if (bits(machInst, 10) == 1) { if (bits(machInst, 23, 22)) return new Unknown64(machInst); diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index 72b7e28..c200da7 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -39,9 +39,9 @@ // AdvSIMD three same template <typename DecoderFeatures> StaticInstPtr decodeNeon3Same(ExtMachInst machInst); - // AdvSIMD three same Extra + // AdvSIMD three register extension template <typename DecoderFeatures> - StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst); + StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst); // AdvSIMD three different inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst); // AdvSIMD two-reg misc @@ -507,7 +507,7 @@ template <typename DecoderFeatures> StaticInstPtr - decodeNeon3SameExtra(ExtMachInst machInst) + decodeNeon3RegExtension(ExtMachInst machInst) { uint8_t q = bits(machInst, 30); uint8_t size = bits(machInst, 23, 22); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f Gerrit-Change-Number: 70724 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Andreas Sandberg <andreas.sandberg@arm.com> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>