Hello all, I am using gem5 in research to evaluate performance effects of a proposed design for multi-socket platforms. I want to simulate custom memory access latencies for 1) a socket accessing the memory it is directly connected with and 2) memory that it would have to access by calling over the processor interconnect to the socket that the target physical address is connected to. My initial plan for implementing this is to establish a mapping of socket <-> address range, and modify the MemCtrl (C++) class' logic to assign different latencies to the memory access depending on if the requesting socket is accessing its own memory or another socket's memory. From this thread and its reply: https://www.mail-archive.com/gem5-users@gem5.org/msg21144.html I was directed to the "dataRequestorId()" and "instRequestorId()" functions in src/cpu/base.hh However, these IDs seem to be assigned at simulation runtime, complicating address range assignment. Is there a way to statically assign a given socket to a given address range in the config.py file? Thank you, -James Pangia