Hi The following interrupt control definition doesn't seem to work for RISCV builds, while it does for X86. system.cpu.createInterruptController()system.cpu.interrupts[0].pio                    = system.membus.mem_side_portssystem.cpu.interrupts[0].int_requestor    = system.membus.cpu_side_portssystem.cpu.interrupts[0].int_responder   = system.membus.mem_side_ports Wondering if there is any name/type change. Could you point me to relevant documents. regardsRobert K

Hi Robert, The documents says: > Connecting the PIO and interrupt ports to the memory bus is an > x86-specific requirement. Other ISAs (e.g., ARM) do not require these 3 > extra lines. See: https://www.gem5.org/documentation/learning_gem5/part1/simple_config/ BR, Zhong Robert Kingsly via gem5-users <gem5-users@gem5.org> 于2025年3月11日周二 17:00写道： > Hi > > The following interrupt control definition doesn't seem to work for RISCV > builds, while it does for X86. > > system.cpu.createInterruptController() > system.cpu.interrupts[0].pio = > system.membus.mem_side_ports > system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports > system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports > > > Wondering if there is any name/type change. Could you point me to relevant > documents. > > regards > Robert K > > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-leave@gem5.org >