bool aligned = pc.instAddr() % sizeof(machInst) == 0;
  if (aligned) {

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68417?usp=email ) Change subject: arch-riscv: refactor bitfields of insts ...................................................................... arch-riscv: refactor bitfields of insts + move bitfields of ExtMachInst defined in bitfields.hh to types.hh Change-Id: Ic25e2fd1a887f87231268a4449d8755593919a0f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68417 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-by: Roger Chang <rogerycchang@google.com> --- M src/arch/riscv/decoder.cc M src/arch/riscv/insts/amo.cc D src/arch/riscv/insts/bitfields.hh M src/arch/riscv/insts/mem.cc M src/arch/riscv/insts/standard.hh M src/arch/riscv/insts/unknown.hh M src/arch/riscv/isa/bitfields.isa M src/arch/riscv/isa/decoder.isa M src/arch/riscv/types.hh M util/m5/src/abi/riscv/m5op.S 10 files changed, 151 insertions(+), 55 deletions(-) Approvals: Roger Chang: Looks good to me, approved Bobby Bruce: Looks good to me, approved kokoro: Regressions pass Hoa Nguyen: Looks good to me, approved diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index b816c17..7faa310 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc @@ -42,6 +42,7 @@ { aligned = true; mid = false; + machInst = 0; emi = 0; } @@ -58,20 +59,20 @@ bool aligned = pc.instAddr() % sizeof(machInst) == 0; if (aligned) { - emi = inst; - if (compressed(emi)) - emi = bits(emi, mid_bit, 0); + emi.instBits = inst; + if (compressed(inst)) + emi.instBits = bits(inst, mid_bit, 0); outOfBytes = !compressed(emi); instDone = true; } else { if (mid) { - assert(bits(emi, max_bit, mid_bit + 1) == 0); - replaceBits(emi, max_bit, mid_bit + 1, inst); + assert(bits(emi.instBits, max_bit, mid_bit + 1) == 0); + replaceBits(emi.instBits, max_bit, mid_bit + 1, inst); mid = false; outOfBytes = false; instDone = true; } else { - emi = bits(inst, max_bit, mid_bit + 1); + emi.instBits = bits(inst, max_bit, mid_bit + 1); mid = !compressed(emi); outOfBytes = true; instDone = compressed(emi); @@ -83,7 +84,7 @@ Decoder::decode(ExtMachInst mach_inst, Addr addr) { DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n", - mach_inst, addr); + mach_inst.instBits, addr); StaticInstPtr &si = instMap[mach_inst]; if (!si) diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc index d845c91..052586e 100644 --- a/src/arch/riscv/insts/amo.cc +++ b/src/arch/riscv/insts/amo.cc @@ -32,7 +32,6 @@ #include <sstream> #include <string> -#include "arch/riscv/insts/bitfields.hh" #include "arch/riscv/utility.hh" #include "cpu/exec_context.hh" #include "cpu/static_inst.hh" @@ -49,7 +48,7 @@ Addr pc, const loader::SymbolTable *symtab) const { std::stringstream ss; - ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; + ss << csprintf("0x%08x", machInst.instBits) << ' ' << mnemonic; return ss.str(); } @@ -66,14 +65,14 @@ { std::stringstream ss; ss << mnemonic; - if (AQ || RL) + if (machInst.aq || machInst.rl) ss << '_'; - if (AQ) + if (machInst.aq) ss << "aq"; - if (RL) + if (machInst.rl) ss << "rl"; - ss << ' ' << registerName(intRegClass[RD]) << ", (" - << registerName(intRegClass[RS1]) << ')'; + ss << ' ' << registerName(intRegClass[machInst.rd]) << ", (" + << registerName(intRegClass[machInst.rs1]) << ')'; return ss.str(); } @@ -94,15 +93,15 @@ { std::stringstream ss; ss << mnemonic; - if (AQ || RL) + if (machInst.aq || machInst.rl) ss << '_'; - if (AQ) + if (machInst.aq) ss << "aq"; - if (RL) + if (machInst.rl) ss << "rl"; - ss << ' ' << registerName(intRegClass[RD]) << ", " - << registerName(intRegClass[RS2]) << ", (" - << registerName(intRegClass[RS1]) << ')'; + ss << ' ' << registerName(intRegClass[machInst.rd]) << ", " + << registerName(intRegClass[machInst.rs2]) << ", (" + << registerName(intRegClass[machInst.rs1]) << ')'; return ss.str(); } @@ -124,15 +123,15 @@ { std::stringstream ss; ss << mnemonic; - if (AQ || RL) + if (machInst.aq || machInst.rl) ss << '_'; - if (AQ) + if (machInst.aq) ss << "aq"; - if (RL) + if (machInst.rl) ss << "rl"; - ss << ' ' << registerName(intRegClass[RD]) << ", " - << registerName(intRegClass[RS2]) << ", (" - << registerName(intRegClass[RS1]) << ')'; + ss << ' ' << registerName(intRegClass[machInst.rd]) << ", " + << registerName(intRegClass[machInst.rs2]) << ", (" + << registerName(intRegClass[machInst.rs1]) << ')'; return ss.str(); } diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh deleted file mode 100644 index 7b985dc..0000000 --- a/src/arch/riscv/insts/bitfields.hh +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __ARCH_RISCV_BITFIELDS_HH__ -#define __ARCH_RISCV_BITFIELDS_HH__ - -#include "base/bitfield.hh" - -#define CSRIMM bits(machInst, 19, 15) -#define FUNCT12 bits(machInst, 31, 20) -#define IMM5 bits(machInst, 11, 7) -#define IMM7 bits(machInst, 31, 25) -#define IMMSIGN bits(machInst, 31) -#define OPCODE bits(machInst, 6, 0) - -#define AQ bits(machInst, 26) -#define RD bits(machInst, 11, 7) -#define RL bits(machInst, 25) -#define RS1 bits(machInst, 19, 15) -#define RS2 bits(machInst, 24, 20) - -#endif // __ARCH_RISCV_BITFIELDS_HH__ diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc index 36d6985..5f58a68 100644 --- a/src/arch/riscv/insts/mem.cc +++ b/src/arch/riscv/insts/mem.cc @@ -32,7 +32,6 @@ #include <sstream> #include <string> -#include "arch/riscv/insts/bitfields.hh" #include "arch/riscv/insts/static_inst.hh" #include "arch/riscv/utility.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh index 5b0e8c2..2e7ae8d 100644 --- a/src/arch/riscv/insts/standard.hh +++ b/src/arch/riscv/insts/standard.hh @@ -33,7 +33,6 @@ #include <string> -#include "arch/riscv/insts/bitfields.hh" #include "arch/riscv/insts/static_inst.hh" #include "arch/riscv/regs/misc.hh" #include "cpu/exec_context.hh" @@ -95,7 +94,7 @@ /// Constructor CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : RiscvStaticInst(mnem, _machInst, __opClass), - csr(FUNCT12), uimm(CSRIMM) + csr(_machInst.funct12), uimm(_machInst.csrimm) { if (csr == CSR_SATP) { flags[IsSquashAfter] = true; diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh index 0c2f75e..64f94de 100644 --- a/src/arch/riscv/insts/unknown.hh +++ b/src/arch/riscv/insts/unknown.hh @@ -34,7 +34,6 @@ #include <string> #include "arch/riscv/faults.hh" -#include "arch/riscv/insts/bitfields.hh" #include "arch/riscv/insts/static_inst.hh" #include "cpu/exec_context.hh" #include "cpu/static_inst.hh" @@ -60,14 +59,14 @@ Fault execute(ExecContext *, trace::InstRecord *) const override { - return std::make_shared<UnknownInstFault>(machInst); + return std::make_shared<UnknownInstFault>(machInst.instBits); } std::string generateDisassembly( Addr pc, const loader::SymbolTable *symtab) const override { - return csprintf("unknown opcode %#02x", OPCODE); + return csprintf("unknown opcode %#02x", machInst.opcode); } }; diff --git a/src/arch/riscv/isa/bitfields.isa b/src/arch/riscv/isa/bitfields.isa index 4f58416..8589269 100644 --- a/src/arch/riscv/isa/bitfields.isa +++ b/src/arch/riscv/isa/bitfields.isa @@ -36,7 +36,7 @@ def bitfield RVTYPE rv_type; def bitfield QUADRANT <1:0>; -def bitfield OPCODE <6:2>; +def bitfield OPCODE5 <6:2>; // R-Type def bitfield ALL <31:0>; diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 53d4a4d..58958bb 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -442,7 +442,7 @@ } } } - 0x3: decode OPCODE { + 0x3: decode OPCODE5 { 0x00: decode FUNCT3 { format Load { 0x0: lb({{ diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh index 4aae1a0..1d501dc 100644 --- a/src/arch/riscv/types.hh +++ b/src/arch/riscv/types.hh @@ -57,7 +57,125 @@ // For now, we should be safe using the msbs to store extra information. BitUnion64(ExtMachInst) // Decoder state - Bitfield<63, 62> rv_type; + Bitfield<63, 62> rv_type; + Bitfield<61> compressed; + // More bits for vector extension + Bitfield<57, 41> vl; // [0, 2**16] + Bitfield<40> vill; + SubBitUnion(vtype8, 39, 32) // exclude vill + Bitfield<39> vma; + Bitfield<38> vta; + Bitfield<37, 35> vsew; + Bitfield<34, 32> vlmul; + EndSubBitUnion(vtype8) + // Common + uint32_t instBits; + Bitfield< 1, 0> quadRant; + Bitfield< 6, 2> opcode5; + Bitfield< 6, 0> opcode; + // R-Type + Bitfield<31, 0> all; + Bitfield<11, 7> rd; + Bitfield<14, 12> funct3; + Bitfield<19, 15> rs1; + Bitfield<24, 20> rs2; + Bitfield<31, 25> funct7; + // Bit shifts + Bitfield<30> srType; + Bitfield<24, 20> shamt5; + Bitfield<25, 20> shamt6; + // I-Type + Bitfield<31, 20> imm12; + // Sync + Bitfield<23, 20> succ; + Bitfield<27, 24> pred; + // S-Type + Bitfield<11, 7> imm5; + Bitfield<31, 25> imm7; + // U-Type + Bitfield<31, 12> imm20; + // SB-Type + Bitfield<7> bimm12bit11; + Bitfield<11, 8> bimm12bits4to1; + Bitfield<30, 25> bimm12bits10to5; + Bitfield<31> immsign; + // UJ-Type + Bitfield<30, 21> ujimmbits10to1; + Bitfield<20> ujimmbit11; + Bitfield<19, 12> ujimmbits19to12; + // System + Bitfield<31, 20> funct12; + Bitfield<19, 15> csrimm; + // Floating point + Bitfield<11, 7> fd; + Bitfield<19, 15> fs1; + Bitfield<24, 20> fs2; + Bitfield<31, 27> fs3; + Bitfield<14, 12> round_mode; + Bitfield<24, 20> conv_sgn; + Bitfield<26, 25> funct2; + // AMO + Bitfield<31, 27> amofunct; + Bitfield<26> aq; + Bitfield<25> rl; + // Compressed + Bitfield<15, 13> copcode; + Bitfield<12> cfunct1; + Bitfield<11, 10> cfunct2high; + Bitfield< 6, 5> cfunct2low; + Bitfield<11, 7> rc1; + Bitfield< 6, 2> rc2; + Bitfield< 9, 7> rp1; + Bitfield< 4, 2> rp2; + Bitfield<11, 7> fc1; + Bitfield< 6, 2> fc2; + Bitfield< 4, 2> fp2; + Bitfield<12, 2> cjumpimm; + Bitfield< 5, 3> cjumpimm3to1; + Bitfield<11, 11> cjumpimm4to4; + Bitfield< 2, 2> cjumpimm5to5; + Bitfield< 7, 7> cjumpimm6to6; + Bitfield< 6, 6> cjumpimm7to7; + Bitfield<10, 9> cjumpimm9to8; + Bitfield< 8, 8> cjumpimm10to10; + Bitfield<12> cjumpimmsign; + Bitfield<12, 5> cimm8; + Bitfield<12, 7> cimm6; + Bitfield< 6, 2> cimm5; + Bitfield<12, 10> cimm3; + Bitfield< 6, 5> cimm2; + Bitfield<12> cimm1; + // Pseudo instructions + Bitfield<31, 25> m5func; + // vector + Bitfield<31, 26> vfunct6; + Bitfield<31, 27> vfunct5; + Bitfield<27, 25> vfunct3; + Bitfield<26, 25> vfunct2; + Bitfield<31, 29> nf; + Bitfield<28> mew; + Bitfield<27, 26> mop; + Bitfield<25> vm; + Bitfield<24, 20> lumop; + Bitfield<24, 20> sumop; + Bitfield<14, 12> width; + Bitfield<24, 20> vs2; + Bitfield<19, 15> vs1; + Bitfield<11, 7> vd; + Bitfield<11, 7> vs3; + Bitfield<19, 15> vecimm; + Bitfield<17, 15> simm3; + // vsetvli + Bitfield<31> bit31; + Bitfield<30> bit30; + Bitfield<30, 20> zimm_vsetvli; + // vsetivli + Bitfield<31, 30> bit31_30; + Bitfield<29, 20> zimm_vsetivli; + Bitfield<19, 15> uimm_vsetivli; + // vsetvl + Bitfield<31, 25> bit31_25; + EndBitUnion(ExtMachInst) } // namespace RiscvISA diff --git a/util/m5/src/abi/riscv/m5op.S b/util/m5/src/abi/riscv/m5op.S index babe854..1b0376a 100644 --- a/util/m5/src/abi/riscv/m5op.S +++ b/util/m5/src/abi/riscv/m5op.S @@ -39,7 +39,7 @@ #include <gem5/asm/generic/m5ops.h> // riscv pseudo instructions have bit 1:0 (QUADRANT) = 0x3, -// bit 6:2 (OPCODE) = 0x1e, and bit 31:25 (M5FUNC) specifies +// bit 6:2 (OPCODE5) = 0x1e, and bit 31:25 (M5FUNC) specifies // the function performed by pseudo instruction .macro m5op_func, name, func -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68417?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic25e2fd1a887f87231268a4449d8755593919a0f Gerrit-Change-Number: 68417 Gerrit-PatchSet: 8 Gerrit-Owner: 轩胡 <huxuan0307@gmail.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Hoa Nguyen <hoanguyen@ucdavis.edu> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>