https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email

  switch (unflattenMiscReg(idx)) {

Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email to review the following change. Change subject: arch-arm: Implement RES0/RES1 with miscreg specifiers ...................................................................... arch-arm: Implement RES0/RES1 with miscreg specifiers Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 29 insertions(+), 73 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index bef2db5..ab6e3f7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -421,11 +421,6 @@ idx = redirectRegVHE(idx); switch (unflattenMiscReg(idx)) { - case MISCREG_HCR: - case MISCREG_HCR2: - if (!release->has(ArmExtension::VIRTUALIZATION)) - return 0; - break; case MISCREG_CPACR: { const uint32_t ones = (uint32_t)(-1); @@ -456,10 +451,6 @@ case MISCREG_MPIDR: case MISCREG_MPIDR_EL1: return readMPIDR(system, tc); - case MISCREG_VMPIDR: - case MISCREG_VMPIDR_EL2: - // top bit defined as RES1 - return readMiscRegNoEffect(idx) | 0x80000000; case MISCREG_ID_AFR0: // not implemented, so alias MIDR case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: @@ -568,10 +559,6 @@ { return miscRegs[MISCREG_CPSR] & 0x800000; } - case MISCREG_SVCR: - { - return miscRegs[MISCREG_SVCR]; - } case MISCREG_L2CTLR: { // mostly unimplemented, just set NumCPUs field from sim and return @@ -594,20 +581,17 @@ } case MISCREG_HCPTR: { - RegVal val = readMiscRegNoEffect(idx); - // The trap bit associated with CP14 is defined as RAZ - val &= ~(1 << 14); - // If a CP bit in NSACR is 0 then the corresponding bit in - // HCPTR is RAO/WI + HCPTR val = readMiscRegNoEffect(idx); bool secure_lookup = release->has(ArmExtension::SECURITY) && isSecure(tc); if (!secure_lookup) { - RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); - val |= (mask ^ 0x7FFF) & 0xBFFF; + NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); + if (!nsacr.cp10) { + val.tcp10 = 1; + val.tcp11 = 1; + } } - // Set the bits for unimplemented coprocessors to RAO/WI - val |= 0x33FF; - return (val); + return val; } case MISCREG_HDFAR: // alias for secure DFAR return readMiscRegNoEffect(MISCREG_DFAR_S); @@ -934,16 +918,10 @@ (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); } break; - case MISCREG_HCR2: - if (!release->has(ArmExtension::VIRTUALIZATION)) - return; - break; case MISCREG_HCR: { const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); selfDebug->setenableTDETGE((HCR)val, mdcr); - if (!release->has(ArmExtension::VIRTUALIZATION)) - return; } break; @@ -1016,31 +994,6 @@ case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1: selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val); break; - case MISCREG_IFSR: - { - // ARM ARM (ARM DDI 0406C.b) B4.1.96 - const uint32_t ifsrMask = - mask(31, 13) | mask(11, 11) | mask(8, 6); - newVal = newVal & ~ifsrMask; - } - break; - case MISCREG_DFSR: - { - // ARM ARM (ARM DDI 0406C.b) B4.1.52 - const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); - newVal = newVal & ~dfsrMask; - } - break; - case MISCREG_AMAIR0: - case MISCREG_AMAIR1: - { - // ARM ARM (ARM DDI 0406C.b) B4.1.5 - // Valid only with LPAE - if (!release->has(ArmExtension::LPAE)) - return; - DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); - } - break; case MISCREG_SCR: getMMUPtr(tc)->invalidateMiscReg(); break; @@ -1327,21 +1280,6 @@ idx = MISCREG_CPSR; } break; - case MISCREG_SVCR: - { - SVCR svcr = miscRegs[MISCREG_SVCR]; - SVCR newSvcr = newVal; - - // Don't allow other bits to be set - svcr.sm = newSvcr.sm; - svcr.za = newSvcr.za; - newVal = svcr; - } - break; - case MISCREG_SMPRI_EL1: - // Only the bottom 4 bits are settable - newVal = newVal & 0xF; - break; case MISCREG_AT_S1E1R_Xt: addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val); return; diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 6f918b2..9203810 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2662,6 +2662,7 @@ .reset(midr) .hyp().monNonSecure(); InitReg(MISCREG_VMPIDR) + .res1(mask(31, 31)) .hyp().monNonSecure(); InitReg(MISCREG_SCTLR) .banked() @@ -2739,13 +2740,17 @@ .hyp().monNonSecure(); InitReg(MISCREG_HCR) .hyp().monNonSecure() - .res0(0x90000000); + .res0(release->has(ArmExtension::VIRTUALIZATION) ? + 0x90000000 : mask(31, 0)); InitReg(MISCREG_HCR2) .hyp().monNonSecure() - .res0(0xffa9ff8c); + .res0(release->has(ArmExtension::VIRTUALIZATION) ? + 0xffa9ff8c : mask(31, 0)); InitReg(MISCREG_HDCR) .hyp().monNonSecure(); InitReg(MISCREG_HCPTR) + .res0(mask(29, 21) | mask(19, 16) | mask(14, 14)) + .res1(mask(13, 12) | mask(9, 0)) .hyp().monNonSecure(); InitReg(MISCREG_HSTR) .hyp().monNonSecure(); @@ -2794,7 +2799,8 @@ .bankedChild() .secure().exceptUserMode(); InitReg(MISCREG_DFSR) - .banked(); + .banked() + .res0(mask(31, 14) | mask(8, 8)); InitReg(MISCREG_DFSR_NS) .bankedChild() .privSecure(!aarch32EL3) @@ -2803,7 +2809,8 @@ .bankedChild() .secure().exceptUserMode(); InitReg(MISCREG_IFSR) - .banked(); + .banked() + .res0(mask(31, 13) | mask(11, 11) | mask(8, 6)); InitReg(MISCREG_IFSR_NS) .bankedChild() .privSecure(!aarch32EL3) @@ -3118,6 +3125,7 @@ .bankedChild() .secure().exceptUserMode(); InitReg(MISCREG_AMAIR0) + .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0)) .banked(); InitReg(MISCREG_AMAIR0_NS) .bankedChild() @@ -3127,6 +3135,7 @@ .bankedChild() .secure().exceptUserMode(); InitReg(MISCREG_AMAIR1) + .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0)) .banked(); InitReg(MISCREG_AMAIR1_NS) .bankedChild() @@ -3976,6 +3985,8 @@ .mapsTo(MISCREG_VPIDR); InitReg(MISCREG_VMPIDR_EL2) .hyp().mon() + .res0(mask(63, 40) | mask(29, 25)) + .res1(mask(31, 31)) .mapsTo(MISCREG_VMPIDR); InitReg(MISCREG_SCTLR_EL1) .allPrivileges().exceptUserMode() @@ -5263,6 +5274,12 @@ }()) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_SVCR) + .res0([](){ + SVCR svcr_mask = 0; + svcr_mask.sm = 1; + svcr_mask.za = 1; + return ~svcr_mask; + }()) .allPrivileges(); InitReg(MISCREG_SMIDR_EL1) .reset([](){ @@ -5274,6 +5291,7 @@ }()) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_SMPRI_EL1) + .res0(mask(63, 4)) .allPrivileges().exceptUserMode().reads(1); InitReg(MISCREG_SMPRIMAP_EL2) .hyp().mon(); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894 Gerrit-Change-Number: 70563 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Attention: Richard Cooper <richard.cooper@arm.com>