Richard Cooper has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70417?usp=email ) Change subject: arch-arm: Add support to exit the simloop on PMU control ...................................................................... arch-arm: Add support to exit the simloop on PMU control PMU enables/disables/resets are often used to identify and demark regions of interest in a workload intended for sampled simulation (e.g. fast-forward, warm-up, detailed simulation). This patch adds the option to exit the simulation loop when these events occur so additional simulation control can be effected (e.g. stats dump/reset, CPU switch, etc). Original patch by Nicholas Lindsay <Nicholas.Lindsey@arm.com>. Updated by Richard Cooper <richard.cooper@arm.com>. Change-Id: I19be0def8d52fa036a3eee6bafeb63cc1f41694a Signed-off-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70417 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/arch/arm/ArmPMU.py M src/arch/arm/pmu.cc M src/arch/arm/pmu.hh M src/python/gem5/simulate/exit_event.py 4 files changed, 40 insertions(+), 5 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Bobby Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py index 3eaed07..a07239b 100644 --- a/src/arch/arm/ArmPMU.py +++ b/src/arch/arm/ArmPMU.py @@ -1,5 +1,5 @@ # -*- mode:python -*- -# Copyright (c) 2009-2014, 2017, 2020, 2022 Arm Limited +# Copyright (c) 2009-2014, 2017-2018, 2020, 2022-2023 Arm Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -215,11 +215,14 @@ platform = Param.Platform(Parent.any, "Platform this device is part of.") eventCounters = Param.Int(31, "Number of supported PMU counters") interrupt = Param.ArmInterruptPin("PMU interrupt") + exitOnPMUControl = Param.Bool( + False, "Exit on PMU enable, disable, or reset" + ) # 64-bit PMU event counters are officially supported when # Armv8.5-A FEAT_PMUv3p5 is implemented. This parameter is not a # full implementation of FEAT_PMUv3p5. use64bitCounters = Param.Bool( False, - "Choose whether to use 64-bit or " "32-bit PMEVCNTR<n>_EL0 registers.", + "Choose whether to use 64-bit or 32-bit PMEVCNTR<n>_EL0 registers.", ) diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc index 89dc2c8..efd6417 100644 --- a/src/arch/arm/pmu.cc +++ b/src/arch/arm/pmu.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014, 2017-2019, 2022 Arm Limited + * Copyright (c) 2011-2014, 2017-2019, 2022-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -46,6 +46,7 @@ #include "dev/arm/base_gic.hh" #include "dev/arm/generic_timer.hh" #include "params/ArmPMU.hh" +#include "sim/sim_exit.hh" namespace gem5 { @@ -66,7 +67,8 @@ cycleCounterEventId(p.cycleEventId), swIncrementEvent(nullptr), reg_pmcr_conf(0), - interrupt(nullptr) + interrupt(nullptr), + exitOnPMUControl(p.exitOnPMUControl) { DPRINTF(PMUVerbose, "Initializing the PMU.\n"); @@ -412,6 +414,21 @@ if (reg_pmcr.d != val.d) clock_remainder = 0; + // Optionally exit the simulation on various PMU control events. + // Exit on enable/disable takes precedence over exit on reset. + if (exitOnPMUControl) { + if (!reg_pmcr.e && val.e) { + inform("Exiting simulation: PMU enable detected"); + exitSimLoop("performance counter enabled", 0); + } else if (reg_pmcr.e && !val.e) { + inform("Exiting simulation: PMU disable detected"); + exitSimLoop("performance counter disabled", 0); + } else if (val.p) { + inform("Exiting simulation: PMU reset detected"); + exitSimLoop("performance counter reset", 0); + } + } + reg_pmcr = val & reg_pmcr_wr_mask; updateAllCounters(); } diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh index ec60c6b..4999031 100644 --- a/src/arch/arm/pmu.hh +++ b/src/arch/arm/pmu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014, 2017-2018, 2022 Arm Limited + * Copyright (c) 2011-2014, 2017-2018, 2022-2023 Arm Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -632,6 +632,12 @@ * List of event types supported by this PMU. */ std::map<EventTypeId, std::shared_ptr<PMUEvent>> eventMap; + + /** + * Exit simloop on PMU reset or disable + */ + const bool exitOnPMUControl; + }; } // namespace ArmISA diff --git a/src/python/gem5/simulate/exit_event.py b/src/python/gem5/simulate/exit_event.py index 605fb6e..61462e4 100644 --- a/src/python/gem5/simulate/exit_event.py +++ b/src/python/gem5/simulate/exit_event.py @@ -49,6 +49,9 @@ ) SIMPOINT_BEGIN = "simpoint begins" MAX_INSTS = "number of instructions reached" + PERF_COUNTER_ENABLE = "performance counter enabled" + PERF_COUNTER_DISABLE = "performance counter disabled" + PERF_COUNTER_RESET = "performance counter reset" @classmethod def translate_exit_status(cls, exit_string: str) -> "ExitEvent": @@ -90,6 +93,12 @@ return ExitEvent.SIMPOINT_BEGIN elif exit_string == "a thread reached the max instruction count": return ExitEvent.MAX_INSTS + elif exit_string == "performance counter enabled": + return ExitEvent.PERF_COUNTER_ENABLE + elif exit_string == "performance counter disabled": + return ExitEvent.PERF_COUNTER_DISABLE + elif exit_string == "performance counter reset": + return ExitEvent.PERF_COUNTER_RESET elif exit_string.endswith("will terminate the simulation.\n"): # This is for the traffic generator exit event return ExitEvent.EXIT -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70417?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I19be0def8d52fa036a3eee6bafeb63cc1f41694a Gerrit-Change-Number: 70417 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Cooper <richard.cooper@arm.com> Gerrit-Reviewer: Andreas Sandberg <andreas.sandberg@arm.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>