https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email

        case MISCREG_FPSCR:

Attention is currently required from: Richard Cooper. Hello Richard Cooper, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email to review the following change. Change subject: arch-arm: Simplify FPSCR writes ...................................................................... arch-arm: Simplify FPSCR writes The old logic was setting up a mask which was covering pretty much the entire register, except for the FPSCR[14:13] and FPSCR[6:5] register fields. Those RES0 fields were treated as WI. We simplify this by explicitly marking them as RES0 at construction time Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> --- M src/arch/arm/isa.cc M src/arch/arm/regs/misc.cc 2 files changed, 2 insertions(+), 32 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 83df61f..9c8e282 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -815,38 +815,7 @@ return; case MISCREG_FPSCR: - { - const uint32_t ones = (uint32_t)(-1); - FPSCR fpscrMask = 0; - fpscrMask.ioc = ones; - fpscrMask.dzc = ones; - fpscrMask.ofc = ones; - fpscrMask.ufc = ones; - fpscrMask.ixc = ones; - fpscrMask.idc = ones; - fpscrMask.ioe = ones; - fpscrMask.dze = ones; - fpscrMask.ofe = ones; - fpscrMask.ufe = ones; - fpscrMask.ixe = ones; - fpscrMask.ide = ones; - fpscrMask.len = ones; - fpscrMask.fz16 = ones; - fpscrMask.stride = ones; - fpscrMask.rMode = ones; - fpscrMask.fz = ones; - fpscrMask.dn = ones; - fpscrMask.ahp = ones; - fpscrMask.qc = ones; - fpscrMask.v = ones; - fpscrMask.c = ones; - fpscrMask.z = ones; - fpscrMask.n = ones; - newVal = (newVal & (uint32_t)fpscrMask) | - (readMiscRegNoEffect(MISCREG_FPSCR) & - ~(uint32_t)fpscrMask); - tc->getDecoderPtr()->as<Decoder>().setContext(newVal); - } + tc->getDecoderPtr()->as<Decoder>().setContext(newVal); break; case MISCREG_FPSR: { diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 9203810..2d76143 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -2199,6 +2199,7 @@ .reset(p.fpsid) .allPrivileges(); InitReg(MISCREG_FPSCR) + .res0(mask(14, 13) | mask(6, 5)) .allPrivileges(); InitReg(MISCREG_MVFR1) .reset([] () { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Gerrit-Change-Number: 70565 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Attention: Richard Cooper <richard.cooper@arm.com>