Gem5-Users, Apologies if this is a silly question or one that has been asked many times before. I've done some quick google searches and haven't found anything yet. I'm a new user to Gem5, and I have gone through a good portion of the tutorial to where I can create various caches with various configurations, memory systems, etc., and connect them all together. So, it seems like, from creating a Python configuration file alone, I would be able to string together something reasonable for describing different RISCV system architectures. This is all good. Perhaps I am naïve, but it seems like the only important thing I'm missing from the base package and what I've learned from the tutorial is where to get specific CPU core implementations / models. For example, when I look at a list from the built-in "se.py" script, there are only a few specific CPU models provided by Gem5: prompt> riscv-gem5 ./configs/example/se.py --list-cpu-types gem5 Simulator System. https://www.gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 version 22.1.0.0 gem5 compiled Jun 24 2023 11:18:42 gem5 started Jun 25 2023 08:54:33 gem5 executing on lvablnode16, pid 96252 command line: riscv-gem5 /dept/Boston/avose/riscv/tools/source/gem5/configs/example/se.py --list-cpu-types Available BaseCPU classes: AtomicSimpleCPU Simple CPU model executing a configurable number of instructions per cycle. This model uses the simplified 'atomic' memory mode. BaseAtomicSimpleCPU Simple CPU model executing a configurable number of instructions per cycle. This model uses the simplified 'atomic' memory mode. BaseMinorCPU BaseNonCachingSimpleCPU Simple CPU model based on the atomic CPU. Unlike the atomic CPU, this model causes the memory system to bypass caches and is therefore slightly faster in some cases. However, its main purpose is as a substitute for hardware virtualized CPUs when stress-testing the memory system. BaseO3CPU BaseTimingSimpleCPU DerivO3CPU MinorCPU NonCachingSimpleCPU Simple CPU model based on the atomic CPU. Unlike the atomic CPU, this model causes the memory system to bypass caches and is therefore slightly faster in some cases. However, its main purpose is as a substitute for hardware virtualized CPUs when stress-testing the memory system. O3CPU RiscvAtomicSimpleCPU Simple CPU model executing a configurable number of instructions per cycle. This model uses the simplified 'atomic' memory mode. RiscvMinorCPU RiscvNonCachingSimpleCPU Simple CPU model based on the atomic CPU. Unlike the atomic CPU, this model causes the memory system to bypass caches and is therefore slightly faster in some cases. However, its main purpose is as a substitute for hardware virtualized CPUs when stress-testing the memory system. RiscvO3CPU RiscvTimingSimpleCPU TimingSimpleCPU I guess I'm wondering how people manage to get a RISC-V "Rocket" or a "Boom" core to be used in place of these available built-in CPU types. Is the idea that one would write the models for the different RISC-V CPUs themselves using the Python / C++ interface, or are there existing core models made available somewhere that people like me could directly use instead? Or, perhaps, are the above CPU core models parameterized sufficiently that they can be made to look something like a "Rocket" or a "Boom v3" core? I will continue to read through the documentation and tutorials. I was just hoping someone might be able to point me in the right direction. Thanks much, ~Aaron Vose