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[XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value

GT
Giacomo Travaglini (Gerrit)
Thu, May 11, 2023 8:25 AM

Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email )

Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset
value
......................................................................

arch-arm: Replace 0ing of miscRegs with assignment of reset value

The reset variable in the MiscRegLUTEntry class defines the per-register
reset value. Rather than simply zeroing the misc registers we should
assign them their reset value when clearing them.

As of now the reset variable is unused so using it is functionally
equivalent of calling memset. This will however change once we start
using the reset field

Signed-off-by: Giacomo Travaglini giacomo.travaglini@arm.com
Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Reviewed-by: Richard Cooper richard.cooper@arm.com
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70457
Tested-by: kokoro noreply+kokoro@google.com
Reviewed-by: Jason Lowe-Power power.jg@gmail.com
Maintainer: Jason Lowe-Power power.jg@gmail.com

M src/arch/arm/isa.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
Richard Cooper: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index aec8243..5a0dec5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -141,7 +141,9 @@
}

  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
  • memset(miscRegs, 0, sizeof(miscRegs));
  • for (auto idx = 0; idx < NUM_MISCREGS; idx++) {

  •    miscRegs[idx] = lookUpMiscReg[idx].reset();
    
  • }

    initID32(p);
    

--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Gerrit-Change-Number: 70457
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini giacomo.travaglini@arm.com
Gerrit-Reviewer: Andreas Sandberg andreas.sandberg@arm.com
Gerrit-Reviewer: Giacomo Travaglini giacomo.travaglini@arm.com
Gerrit-Reviewer: Jason Lowe-Power power.jg@gmail.com
Gerrit-Reviewer: Richard Cooper richard.cooper@arm.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email ) Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset value ...................................................................... arch-arm: Replace 0ing of miscRegs with assignment of reset value The reset variable in the MiscRegLUTEntry class defines the per-register reset value. Rather than simply zeroing the misc registers we should assign them their reset value when clearing them. As of now the reset variable is unused so using it is functionally equivalent of calling memset. This will however change once we start using the reset field Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79 Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70457 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> --- M src/arch/arm/isa.cc 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index aec8243..5a0dec5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -141,7 +141,9 @@ } SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; - memset(miscRegs, 0, sizeof(miscRegs)); + for (auto idx = 0; idx < NUM_MISCREGS; idx++) { + miscRegs[idx] = lookUpMiscReg[idx].reset(); + } initID32(p); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79 Gerrit-Change-Number: 70457 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Andreas Sandberg <andreas.sandberg@arm.com> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>