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[S] Change in gem5/gem5[develop]: arch-riscv,dev: Remove CLINT parameter of HiFiveBase

RC
Roger Chang (Gerrit)
Thu, Mar 16, 2023 8:07 AM

Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69017?usp=email )

Change subject: arch-riscv,dev: Remove CLINT parameter of HiFiveBase
......................................................................

arch-riscv,dev: Remove CLINT parameter of HiFiveBase

Remove the clint parameter because HiFiveBase platform don't need
to use CLINT component

Change-Id: Iea4c8c54354b8230f1352d0ae31a6a6a3a479ff4

M src/dev/riscv/HiFive.py
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
3 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 5bd6363..e58fcff 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -72,13 +72,6 @@
board series. It contains the CLINT and PLIC
interrupt controllers, Uart and Disk.

  • Driving CLINT:
  •    CLINT has an interrupt pin which increments
    
  •    mtime. It can be connected to any interrupt
    
  •    source pin which acts as the RTCCLK pin. An
    
  •    abstract RTC wrapper called RiscvRTC can be
    
  •    used.
    
  • Driving PLIC:
        PLIC handles external interrupts. Interrupt
        PioDevices should inherit from PlicIntDevice
    

@@ -94,9 +87,6 @@
cxx_header = "dev/riscv/hifive.hh"
cxx_class = "gem5::HiFiveBase"

  • CLINT

  • clint = Param.Clint(NULL, "CLINT")
  • # PLIC
    plic = Param.PlicBase(NULL, "PLIC")
    

@@ -159,6 +149,13 @@
setup for a RISC-V HiFive platform. See
configs/example/riscv/fs_linux.py for example.

  • Driving CLINT:
  •    CLINT has an interrupt pin which increments
    
  •    mtime. It can be connected to any interrupt
    
  •    source pin which acts as the RTCCLK pin. An
    
  •    abstract RTC wrapper called RiscvRTC can be
    
  •    used.
    
  • Uart:
        The HiFive platform also has an uart_int_id.
        This is because Uart8250 uses postConsoleInt
    

diff --git a/src/dev/riscv/hifive.cc b/src/dev/riscv/hifive.cc
index 0487eab..ca44a79 100644
--- a/src/dev/riscv/hifive.cc
+++ b/src/dev/riscv/hifive.cc
@@ -50,10 +50,9 @@

HiFiveBase::HiFiveBase(const Params &params) :
Platform(params),

  • clint(params.clint), plic(params.plic),
  • plic(params.plic),
    uartIntID(params.uart_int_id)
    {
  • fatal_if(clint == nullptr, "CLINT should not be NULL");
    fatal_if(plic == nullptr, "PLIC should not be NULL");
    }

diff --git a/src/dev/riscv/hifive.hh b/src/dev/riscv/hifive.hh
index 99d7ae6..2b17715 100644
--- a/src/dev/riscv/hifive.hh
+++ b/src/dev/riscv/hifive.hh
@@ -52,7 +52,6 @@
class HiFiveBase : public Platform
{
public:

  • Clint *clint;
    PlicBase *plic;
    int uartIntID;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iea4c8c54354b8230f1352d0ae31a6a6a3a479ff4
Gerrit-Change-Number: 69017
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang rogerycchang@google.com
Gerrit-MessageType: newchange

Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69017?usp=email ) Change subject: arch-riscv,dev: Remove CLINT parameter of HiFiveBase ...................................................................... arch-riscv,dev: Remove CLINT parameter of HiFiveBase Remove the clint parameter because HiFiveBase platform don't need to use CLINT component Change-Id: Iea4c8c54354b8230f1352d0ae31a6a6a3a479ff4 --- M src/dev/riscv/HiFive.py M src/dev/riscv/hifive.cc M src/dev/riscv/hifive.hh 3 files changed, 8 insertions(+), 13 deletions(-) diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py index 5bd6363..e58fcff 100755 --- a/src/dev/riscv/HiFive.py +++ b/src/dev/riscv/HiFive.py @@ -72,13 +72,6 @@ board series. It contains the CLINT and PLIC interrupt controllers, Uart and Disk. - Driving CLINT: - CLINT has an interrupt pin which increments - mtime. It can be connected to any interrupt - source pin which acts as the RTCCLK pin. An - abstract RTC wrapper called RiscvRTC can be - used. - Driving PLIC: PLIC handles external interrupts. Interrupt PioDevices should inherit from PlicIntDevice @@ -94,9 +87,6 @@ cxx_header = "dev/riscv/hifive.hh" cxx_class = "gem5::HiFiveBase" - # CLINT - clint = Param.Clint(NULL, "CLINT") - # PLIC plic = Param.PlicBase(NULL, "PLIC") @@ -159,6 +149,13 @@ setup for a RISC-V HiFive platform. See configs/example/riscv/fs_linux.py for example. + Driving CLINT: + CLINT has an interrupt pin which increments + mtime. It can be connected to any interrupt + source pin which acts as the RTCCLK pin. An + abstract RTC wrapper called RiscvRTC can be + used. + Uart: The HiFive platform also has an uart_int_id. This is because Uart8250 uses postConsoleInt diff --git a/src/dev/riscv/hifive.cc b/src/dev/riscv/hifive.cc index 0487eab..ca44a79 100644 --- a/src/dev/riscv/hifive.cc +++ b/src/dev/riscv/hifive.cc @@ -50,10 +50,9 @@ HiFiveBase::HiFiveBase(const Params &params) : Platform(params), - clint(params.clint), plic(params.plic), + plic(params.plic), uartIntID(params.uart_int_id) { - fatal_if(clint == nullptr, "CLINT should not be NULL"); fatal_if(plic == nullptr, "PLIC should not be NULL"); } diff --git a/src/dev/riscv/hifive.hh b/src/dev/riscv/hifive.hh index 99d7ae6..2b17715 100644 --- a/src/dev/riscv/hifive.hh +++ b/src/dev/riscv/hifive.hh @@ -52,7 +52,6 @@ class HiFiveBase : public Platform { public: - Clint *clint; PlicBase *plic; int uartIntID; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/69017?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Iea4c8c54354b8230f1352d0ae31a6a6a3a479ff4 Gerrit-Change-Number: 69017 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Chang <rogerycchang@google.com> Gerrit-MessageType: newchange