Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68697?usp=email )
Change subject: fastmodel: delay the breakpoint event handle to simulation
stop
......................................................................
fastmodel: delay the breakpoint event handle to simulation stop
The fastmodel simulation would be paused when it hits a breakpoint.
However, the order of stop event happens after the breakpoint event. If
we handle the breakpoint logic in the breakpoint event, it may cause
somehow status unsynchronized. To make the behavior stable, we delay the
breakpoint handle until the simulation stop event called.
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 21 insertions(+), 12 deletions(-)
Approvals:
Earl Ou: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 45e020d..462995a 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -269,6 +269,22 @@
return iris::E_ok;
}
- // Handle the breakpoint event at simulation is stopped if needed.
- if (bpAddr.has_value()) {
-
auto it = getOrAllocBp(bpAddr.value());
-
std::shared_ptr<BpInfo::EventList> events = it->second->events;
-
auto e_it = events->begin();
-
while (e_it != events->end()) {
-
PCEvent *e = *e_it;
-
// Advance e_it here since e might remove itself from the list.
-
e_it++;
-
e->process(this);
-
}
-
bpAddr.reset();
- }
-
// If simulation time has stopped for any reason, IRIS helpfully clears
// all stepping counters and we need to set them back. We might also
need
// to service events based on the current number of executed
instructions.
@@ -286,19 +302,10 @@
uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
uint64_t sInstId, bool syncEc, std::string &error_message_out)
{
- // Handle the breakpoint event later when the fastmodel simulation is
- // stopped.
Addr pc = fields.at("PC").getU64();
- bpAddr = pc;
return iris::E_ok;
}
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 05209e6..88c6746 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -31,6 +31,7 @@
#include <list>
#include <map>
#include <memory>
+#include <optional>
#include <unordered_map>
#include "arch/arm/fastmodel/iris/memory_spaces.hh"
@@ -133,6 +134,7 @@
using BpInfoIt = BpInfoMap::iterator;
BpInfoMap bps;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Gerrit-Change-Number: 68697
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang yuhsingw@google.com
Gerrit-Reviewer: Earl Ou shunhsingou@google.com
Gerrit-Reviewer: Gabe Black gabe.black@gmail.com
Gerrit-Reviewer: Wei-Han Chen weihanchen@google.com
Gerrit-Reviewer: Yu-hsin Wang yuhsingw@google.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com
Gerrit-MessageType: merged
Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68697?usp=email )
Change subject: fastmodel: delay the breakpoint event handle to simulation
stop
......................................................................
fastmodel: delay the breakpoint event handle to simulation stop
The fastmodel simulation would be paused when it hits a breakpoint.
However, the order of stop event happens after the breakpoint event. If
we handle the breakpoint logic in the breakpoint event, it may cause
somehow status unsynchronized. To make the behavior stable, we delay the
breakpoint handle until the simulation stop event called.
Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68697
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 21 insertions(+), 12 deletions(-)
Approvals:
Earl Ou: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 45e020d..462995a 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -269,6 +269,22 @@
return iris::E_ok;
}
+ // Handle the breakpoint event at simulation is stopped if needed.
+ if (bpAddr.has_value()) {
+ auto it = getOrAllocBp(bpAddr.value());
+
+ std::shared_ptr<BpInfo::EventList> events = it->second->events;
+ auto e_it = events->begin();
+ while (e_it != events->end()) {
+ PCEvent *e = *e_it;
+ // Advance e_it here since e might remove itself from the list.
+ e_it++;
+ e->process(this);
+ }
+
+ bpAddr.reset();
+ }
+
// If simulation time has stopped for any reason, IRIS helpfully clears
// all stepping counters and we need to set them back. We might also
need
// to service events based on the current number of executed
instructions.
@@ -286,19 +302,10 @@
uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
uint64_t sInstId, bool syncEc, std::string &error_message_out)
{
+ // Handle the breakpoint event later when the fastmodel simulation is
+ // stopped.
Addr pc = fields.at("PC").getU64();
-
- auto it = getOrAllocBp(pc);
-
- std::shared_ptr<BpInfo::EventList> events = it->second->events;
- auto e_it = events->begin();
- while (e_it != events->end()) {
- PCEvent *e = *e_it;
- // Advance e_it here since e might remove itself from the list.
- e_it++;
- e->process(this);
- }
-
+ bpAddr = pc;
return iris::E_ok;
}
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 05209e6..88c6746 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -31,6 +31,7 @@
#include <list>
#include <map>
#include <memory>
+#include <optional>
#include <unordered_map>
#include "arch/arm/fastmodel/iris/memory_spaces.hh"
@@ -133,6 +134,7 @@
using BpInfoIt = BpInfoMap::iterator;
BpInfoMap bps;
+ std::optional<Addr> bpAddr;
BpInfoIt getOrAllocBp(Addr pc);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0083561f561af71370ccaa066220b72ed7831b78
Gerrit-Change-Number: 68697
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang <yuhsingw@google.com>
Gerrit-Reviewer: Earl Ou <shunhsingou@google.com>
Gerrit-Reviewer: Gabe Black <gabe.black@gmail.com>
Gerrit-Reviewer: Wei-Han Chen <weihanchen@google.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsingw@google.com>
Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>
Gerrit-MessageType: merged