Yu-hsin Wang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/65534?usp=email ) Change subject: fastmodel: CortexR52 export standbywfi signal ...................................................................... fastmodel: CortexR52 export standbywfi signal Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1 --- M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc M src/arch/arm/fastmodel/CortexR52/evs.cc M src/arch/arm/fastmodel/CortexR52/evs.hh M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa 8 files changed, 53 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py index 4970ae2..1e267f0 100644 --- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py +++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py @@ -31,7 +31,7 @@ from m5.objects.ArmISA import ArmISA from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket from m5.objects.ResetPort import ResetResponsePort -from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin +from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin from m5.objects.Iris import IrisBaseCPU from m5.objects.SystemC import SystemC_ScModule @@ -56,6 +56,9 @@ "processor logic, including debug logic." ) halt = IntSinkPin("Raising this signal will put the core into halt mode.") + standbywfi = IntSourcePin( + "This signal indicates if a core is in WFI state." + ) CFGEND = Param.Bool( False, diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc index be83082..fdfce2b 100644 --- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc +++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc @@ -99,6 +99,8 @@ // index. Also verify that that index is not being used. assert(idx == InvalidPortID); return evs->gem5_getPort(if_name, num); + } else if (if_name == "standbywfi") { + return evs->gem5_getPort(if_name, num); } else { return SimObject::getPort(if_name, idx); } diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc index 6887c6c..c18c58c 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.cc +++ b/src/arch/arm/fastmodel/CortexR52/evs.cc @@ -79,6 +79,7 @@ core_reset(name + ".core_reset", 0), poweron_reset(name + ".poweron_reset", 0), halt(name + ".halt", 0), + standbywfi(name + ".standbywfi"), cfgvectable((name + "cfgvectable").c_str()) { for (int i = 0; i < Evs::PpiCount; i++) { @@ -88,10 +89,10 @@ core_reset.signal_out.bind(evs->core_reset[cpu]); poweron_reset.signal_out.bind(evs->poweron_reset[cpu]); halt.signal_out.bind(evs->halt[cpu]); + evs->standbywfi[cpu].bind(standbywfi.signal_in); cfgvectable.bind(evs->cfgvectable[cpu]); } - template <class Types> ScxEvsCortexR52<Types>::ScxEvsCortexR52( const sc_core::sc_module_name &mod_name, const Params &p) : @@ -143,6 +144,8 @@ return this->corePins.at(idx)->poweron_reset; } else if (if_name == "halt") { return this->corePins.at(idx)->halt; + } else if (if_name == "standbywfi") { + return this->corePins.at(idx)->standbywfi.signal_out; } else if (if_name == "ext_slave") { return this->ext_slave; } else if (if_name == "top_reset") { diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh index 535d678..5f9a117 100644 --- a/src/arch/arm/fastmodel/CortexR52/evs.hh +++ b/src/arch/arm/fastmodel/CortexR52/evs.hh @@ -83,6 +83,23 @@ template <typename T> using SignalInitiator = amba_pv::signal_master_port<T>; + class SignalReceiverInt : public SignalReceiver + { + public: + IntSourcePin<SignalReceiverInt> signal_out; + + explicit SignalReceiverInt(const std::string &name) + : SignalReceiver(name), + signal_out(name + ".signal_out", 0, this) + { + onChange([this](bool status) { + if (!signal_out.isConnected()) + return; + status ? signal_out.raise() : signal_out.lower(); + }); + } + }; + std::string name; Evs *evs; int cpu; @@ -110,6 +127,7 @@ SignalSender core_reset; SignalSender poweron_reset; SignalSender halt; + SignalReceiverInt standbywfi; SignalInitiator<uint64_t> cfgvectable; }; diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa index 2a7299d..2738ba2 100644 --- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa @@ -53,6 +53,9 @@ self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -79,6 +82,7 @@ slave port<Signal> core_reset[1]; slave port<Signal> poweron_reset[1]; slave port<Signal> halt[1]; + master port<Signal> standbywfi[1]; slave port<Signal> top_reset; slave port<Signal> dbg_reset; slave port<Value_64> cfgvectable[1]; diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa index 9100a5b..485ffee 100644 --- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa @@ -53,6 +53,9 @@ self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -80,6 +83,7 @@ slave port<Signal> core_reset[2]; slave port<Signal> poweron_reset[2]; slave port<Signal> halt[2]; + master port<Signal> standbywfi[2]; slave port<Signal> top_reset; slave port<Signal> dbg_reset; slave port<Value_64> cfgvectable[2]; diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa index bb8d153..1e526d9 100644 --- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa @@ -53,6 +53,9 @@ self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -81,6 +84,7 @@ slave port<Signal> core_reset[3]; slave port<Signal> poweron_reset[3]; slave port<Signal> halt[3]; + master port<Signal> standbywfi[3]; slave port<Signal> top_reset; slave port<Signal> dbg_reset; slave port<Value_64> cfgvectable[3]; diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa index 5b278dd..df23bf1 100644 --- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa +++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa @@ -53,6 +53,9 @@ self.dbg_reset => core.presetdbg; self.halt => core.cpuhalt; + // Status signals. + core.standbywfi => self.standbywfi; + // Clocks. clock1Hz.clk_out => clockDiv.clk_in; clock1Hz.clk_out => clockDivPeriph.clk_in; @@ -82,6 +85,7 @@ slave port<Signal> core_reset[4]; slave port<Signal> poweron_reset[4]; slave port<Signal> halt[4]; + master port<Signal> standbywfi[4]; slave port<Signal> top_reset; slave port<Signal> dbg_reset; slave port<Value_64> cfgvectable[4]; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/65534?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1 Gerrit-Change-Number: 65534 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-hsin Wang <yuhsingw@google.com> Gerrit-MessageType: newchange