Derek C. has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68482?usp=email ) Change subject: stdlib: Use get_mem_ports in incorporate caches ...................................................................... stdlib: Use get_mem_ports in incorporate caches Make use of get_mem_ports() method of the AbstractMemorySystem interface when incorporating caches to prevent the usage of the hard-coded memory port name "port" as some memory controllers do not have a port with this exact name. Change-Id: Ic7480166b257c6d356027234758b65b0a97995e3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68482 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> --- M src/python/gem5/components/cachehierarchies/classic/no_cache.py M src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py 4 files changed, 8 insertions(+), 8 deletions(-) Approvals: Bobby Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/gem5/components/cachehierarchies/classic/no_cache.py b/src/python/gem5/components/cachehierarchies/classic/no_cache.py index f3bbdcd..51b5d30 100644 --- a/src/python/gem5/components/cachehierarchies/classic/no_cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/no_cache.py @@ -119,8 +119,8 @@ # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port def _setup_coherent_io_bridge(self, board: AbstractBoard) -> None: """Create a bridge from I/O back to membus""" diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py index dc44c9e..42ff183 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py @@ -90,8 +90,8 @@ # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port self.l1icaches = [ L1ICache(size=self._l1i_size) diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index f10828b..8b60aef 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -115,8 +115,8 @@ # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port self.l1icaches = [ L1ICache(size=self._l1i_size) diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py index 602c99c..72df1a5 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py @@ -111,8 +111,8 @@ # Set up the system port for functional access from the simulator. board.connect_system_port(self.membus.cpu_side_ports) - for cntr in board.get_memory().get_memory_controllers(): - cntr.port = self.membus.mem_side_ports + for _, port in board.get_memory().get_mem_ports(): + self.membus.mem_side_ports = port self.l1icaches = [ L1ICache( -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68482?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic7480166b257c6d356027234758b65b0a97995e3 Gerrit-Change-Number: 68482 Gerrit-PatchSet: 2 Gerrit-Owner: Derek C. <christ.derek@gmail.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Derek C. <christ.derek@gmail.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-MessageType: merged