gem5-dev@gem5.org

The gem5 Developer List

View all threads

[XS] Change in gem5/gem5[develop]: arch-riscv: Fix WFI for O3 CPU

BB
Bobby Bruce (Gerrit)
Wed, May 17, 2023 5:49 PM

Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70657?usp=email )

Change subject: arch-riscv: Fix WFI for O3 CPU
......................................................................

arch-riscv: Fix WFI for O3 CPU

This commit:
https://gem5-review.googlesource.com/c/public/gem5/+/61511
introduced a bug where the O3 CPU hangs. This is because WFI must be
tagged as IsNonSpeculative, IsQuiesce, and IsSerializeAfter to
function correctly with O3 CPUs.

Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445
Issue-on: https://gem5.atlassian.net/browse/GEM5-1323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70657
Maintainer: Jason Lowe-Power power.jg@gmail.com
Reviewed-by: Roger Chang rogerycchang@google.com
Reviewed-by: Jui-min Lee fcrh@google.com
Reviewed-by: Jason Lowe-Power power.jg@gmail.com
Tested-by: kokoro noreply+kokoro@google.com

M src/arch/riscv/isa/decoder.isa
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Jui-min Lee: Looks good to me, approved
Roger Chang: Looks good to me, but someone else must approve
kokoro: Regressions pass

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index f22efb0..3acd80e 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2278,7 +2278,8 @@
&& xc->readMiscReg(MISCREG_NMIP) == 0) {
tc->quiesce();
}

  •                    }}, No_OpClass);
    
  •                    }}, IsNonSpeculative, IsQuiesce,
    
  •                        IsSerializeAfter, No_OpClass);
                    }
                    0x9: sfence_vma({{
                        STATUS status = xc->readMiscReg(MISCREG_STATUS);
    

--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/70657?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings?usp=email

Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445
Gerrit-Change-Number: 70657
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Jason Lowe-Power power.jg@gmail.com
Gerrit-Reviewer: Jui-min Lee fcrh@google.com
Gerrit-Reviewer: Roger Chang rogerycchang@google.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com

Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70657?usp=email ) Change subject: arch-riscv: Fix WFI for O3 CPU ...................................................................... arch-riscv: Fix WFI for O3 CPU This commit: https://gem5-review.googlesource.com/c/public/gem5/+/61511 introduced a bug where the O3 CPU hangs. This is because WFI must be tagged as `IsNonSpeculative`, `IsQuiesce`, and `IsSerializeAfter` to function correctly with O3 CPUs. Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445 Issue-on: https://gem5.atlassian.net/browse/GEM5-1323 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70657 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Roger Chang <rogerycchang@google.com> Reviewed-by: Jui-min Lee <fcrh@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/arch/riscv/isa/decoder.isa 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Jui-min Lee: Looks good to me, approved Roger Chang: Looks good to me, but someone else must approve kokoro: Regressions pass diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index f22efb0..3acd80e 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -2278,7 +2278,8 @@ && xc->readMiscReg(MISCREG_NMIP) == 0) { tc->quiesce(); } - }}, No_OpClass); + }}, IsNonSpeculative, IsQuiesce, + IsSerializeAfter, No_OpClass); } 0x9: sfence_vma({{ STATUS status = xc->readMiscReg(MISCREG_STATUS); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70657?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445 Gerrit-Change-Number: 70657 Gerrit-PatchSet: 3 Gerrit-Owner: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Jui-min Lee <fcrh@google.com> Gerrit-Reviewer: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>