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Build failed in Jenkins: nightly #566

Bobby Bruce

Wed, Apr 12, 2023 9:49 PM

The following patch should fix this nightly bug:
https://gem5-review.googlesource.com/c/public/gem5/+/69717

There was a small bug introduced where header files were not being added to the “build” directory. This broke the SST compilation as it uses the “build” directory as a include path.

In addition, this patch will also fix the SST Makefile to not use the headers in the “build” directory. I think this is bad practice:
https://gem5-review.googlesource.com/c/public/gem5/+/69718

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net

On Apr 10, 2023, at 3:34 PM, jenkins-no-reply--- via gem5-dev gem5-dev@gem5.org wrote:

See https://jenkins.gem5.org/job/nightly/571/display/redirect?page=changes

Changes:

[gabe.black] base: Add support for unix domain sockets in ListenSocket.

[...truncated 4.44 MB...]
[SO Param] m5.objects.QemuFwCfg, QemuFwCfgMmio -> RISCV/python/_m5/param_QemuFwCfgMmio.cc
[ SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os
[ TRACING] -> RISCV/debug/QemuFwCfg.hh
[ TRACING] -> RISCV/debug/QemuFwCfgVerbose.hh
[ TRACING] -> RISCV/debug/QemuFwCfg.cc
[ SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os
[ TRACING] -> RISCV/debug/QemuFwCfgVerbose.cc
[ SHCXX] RISCV/debug/QemuFwCfg.cc -> .os
[ SHCXX] RISCV/dev/serial/Serial.py.cc -> .os
[ SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os
[SO Param] m5.objects.Serial, SerialDevice -> RISCV/python/_m5/param_SerialDevice.cc
[SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/python/_m5/param_SerialNullDevice.cc
[SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh
[SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/params/SerialNullDevice.hh
[ SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os
[SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc
[ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc
[ SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os
[ SHCXX] RISCV/dev/serial/Uart.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os
[ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh
[SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh
[ SHCXX] RISCV/enums/TerminalDump.cc -> .os
[ SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os
[SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc
[SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh
[ SHCXX] RISCV/python/_m5/param_Uart.cc -> .os
[SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc
[SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh
[ SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os
[SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc
[SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh
[ SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os
[ SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os
[ SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os
[ TRACING] -> RISCV/debug/Terminal.hh
[ TRACING] -> RISCV/debug/TerminalVerbose.hh
[ SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os
[ SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os
[ TRACING] -> RISCV/debug/Uart.hh
[ TRACING] -> RISCV/debug/Terminal.cc
[ SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os
[ SHCXX] RISCV/debug/Terminal.cc -> .os
[ TRACING] -> RISCV/debug/TerminalVerbose.cc
[ SHCXX] RISCV/debug/TerminalVerbose.cc -> .os
[ TRACING] -> RISCV/debug/Uart.cc
[ SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os
[ SHCXX] RISCV/debug/Uart.cc -> .os
[SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc
[SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc
[SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh
[SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh
[ SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os
[SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc
[SO Param] m5.objects.PciDevice, PciBarNone -> RISCV/python/_m5/param_PciBarNone.cc
[ SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os
[ SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os
[ SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os
[ SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os
[SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc
[ SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciLegacyIoBar -> RISCV/python/_m5/param_PciLegacyIoBar.cc
[ SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciMemBar -> RISCV/python/_m5/param_PciMemBar.cc
[SO Param] m5.objects.PciDevice, PciMemUpperBar -> RISCV/python/_m5/param_PciMemUpperBar.cc
[ SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciDevice -> RISCV/python/_m5/param_PciDevice.cc
[ TRACING] -> RISCV/debug/PciDevice.hh
[ TRACING] -> RISCV/debug/PciDevice.cc
[ SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os
[ SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os
[ SHCXX] RISCV/debug/PciDevice.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os
[ SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os
[SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc
[SO Param] m5.objects.PciHost, GenericPciHost -> RISCV/python/_m5/param_GenericPciHost.cc
[ TRACING] -> RISCV/debug/PciHost.hh
[ TRACING] -> RISCV/debug/PciHost.cc
[ SHCXX] src/dev/pci/host.cc -> RISCV/dev/pci/host.os
[ SHCXX] RISCV/debug/PciHost.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciHost.cc -> .os
[ SHCXX] RISCV/python/_m5/param_GenericPciHost.cc -> .os
[ SHCXX] RISCV/dev/pci/CopyEngine.py.cc -> .os
[SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/python/_m5/param_CopyEngine.cc
[ TRACING] -> RISCV/debug/DMACopyEngine.hh
[SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/params/CopyEngine.hh
[ TRACING] -> RISCV/debug/DMACopyEngine.cc
[ SHCXX] RISCV/debug/DMACopyEngine.cc -> .os
[ SHCXX] RISCV/python/_m5/param_CopyEngine.cc -> .os
[ SHCXX] src/dev/pci/copy_engine.cc -> RISCV/dev/pci/copy_engine.os
[ SHCXX] RISCV/dev/lupio/LupioBLK.py.cc -> .os
[SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/python/_m5/param_LupioBLK.cc
[SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/params/LupioBLK.hh
[ TRACING] -> RISCV/debug/LupioBLK.hh
[ SHCXX] RISCV/python/_m5/param_LupioBLK.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioIPI.py.cc -> .os
[SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/python/_m5/param_LupioIPI.cc
[ SHCXX] RISCV/dev/lupio/LupioPIC.py.cc -> .os
[SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/params/LupioIPI.hh
[ SHCXX] RISCV/python/_m5/param_LupioIPI.cc -> .os
[SO Param] m5.objects.LupioPIC, LupioPIC -> RISCV/python/_m5/param_LupioPIC.cc
[ SHCXX] RISCV/python/_m5/param_LupioPIC.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioRNG.py.cc -> .os
[SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/python/_m5/param_LupioRNG.cc
[ SHCXX] RISCV/dev/lupio/LupioRTC.py.cc -> .os
[SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/params/LupioRNG.hh
[ TRACING] -> RISCV/debug/LupioRNG.hh
[ SHCXX] RISCV/python/_m5/param_LupioRNG.cc -> .os
[SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/python/_m5/param_LupioRTC.cc
[SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/params/LupioRTC.hh
[ TRACING] -> RISCV/debug/LupioRTC.hh
[ SHCXX] RISCV/dev/lupio/LupioTMR.py.cc -> .os
[SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/python/_m5/param_LupioTMR.cc
[ SHCXX] RISCV/python/_m5/param_LupioRTC.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioTTY.py.cc -> .os
[SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/params/LupioTMR.hh
[ SHCXX] RISCV/python/_m5/param_LupioTMR.cc -> .os
[SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/python/_m5/param_LupioTTY.cc
[ SHCXX] RISCV/dev/lupio/LupioSYS.py.cc -> .os
[SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/python/_m5/param_LupioSYS.cc
[SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/params/LupioTTY.hh
[ TRACING] -> RISCV/debug/LupioBLK.cc
[ SHCXX] RISCV/debug/LupioBLK.cc -> .os
[SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/params/LupioSYS.hh
[ SHCXX] RISCV/python/_m5/param_LupioTTY.cc -> .os
[ TRACING] -> RISCV/debug/LupioSYS.hh
[ SHCXX] RISCV/python/_m5/param_LupioSYS.cc -> .os
[ TRACING] -> RISCV/debug/LupioIPI.cc
[ TRACING] -> RISCV/debug/LupioIPI.hh
[ SHCXX] RISCV/debug/LupioIPI.cc -> .os
[ TRACING] -> RISCV/debug/LupioPIC.cc
[ TRACING] -> RISCV/debug/LupioPIC.hh
[ SHCXX] RISCV/debug/LupioPIC.cc -> .os
[ TRACING] -> RISCV/debug/LupioRNG.cc
[ TRACING] -> RISCV/debug/LupioRTC.cc
[ SHCXX] RISCV/debug/LupioRNG.cc -> .os
[ SHCXX] RISCV/debug/LupioRTC.cc -> .os
[ TRACING] -> RISCV/debug/LupioTMR.cc
[ TRACING] -> RISCV/debug/LupioTMR.hh
[ SHCXX] RISCV/debug/LupioTMR.cc -> .os
[ TRACING] -> RISCV/debug/LupioTTY.cc
[ TRACING] -> RISCV/debug/LupioSYS.cc
[ TRACING] -> RISCV/debug/LupioTTY.hh
[ SHCXX] RISCV/debug/LupioSYS.cc -> .os
[ SHCXX] src/dev/lupio/lupio_blk.cc -> RISCV/dev/lupio/lupio_blk.os
[ SHCXX] src/dev/lupio/lupio_ipi.cc -> RISCV/dev/lupio/lupio_ipi.os
[ SHCXX] RISCV/debug/LupioTTY.cc -> .os
[ SHCXX] src/dev/lupio/lupio_pic.cc -> RISCV/dev/lupio/lupio_pic.os
[ SHCXX] src/dev/lupio/lupio_rng.cc -> RISCV/dev/lupio/lupio_rng.os
[ SHCXX] src/dev/lupio/lupio_rtc.cc -> RISCV/dev/lupio/lupio_rtc.os
[ SHCXX] src/dev/lupio/lupio_tmr.cc -> RISCV/dev/lupio/lupio_tmr.os
[ SHCXX] src/dev/lupio/lupio_tty.cc -> RISCV/dev/lupio/lupio_tty.os
[ SHCXX] src/dev/lupio/lupio_sys.cc -> RISCV/dev/lupio/lupio_sys.os
[ SHCXX] RISCV/dev/virtio/VirtIO.py.cc -> .os
[SO Param] m5.objects.VirtIO, VirtIODeviceBase -> RISCV/python/_m5/param_VirtIODeviceBase.cc
[ SHCXX] RISCV/python/_m5/param_VirtIODeviceBase.cc -> .os
[SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/python/_m5/param_VirtIODummyDevice.cc
[SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/params/VirtIODummyDevice.hh
[SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/python/_m5/param_PciVirtIO.cc
[ SHCXX] RISCV/dev/virtio/VirtIOConsole.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_VirtIODummyDevice.cc -> .os
[SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/params/PciVirtIO.hh
[ SHCXX] RISCV/python/_m5/param_PciVirtIO.cc -> .os
[SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/python/_m5/param_VirtIOConsole.cc
[ SHCXX] RISCV/dev/virtio/VirtIOBlock.py.cc -> .os
[SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/params/VirtIOConsole.hh
[SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/python/_m5/param_VirtIOBlock.cc
[ SHCXX] RISCV/python/_m5/param_VirtIOConsole.cc -> .os
[SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/params/VirtIOBlock.hh
[ SHCXX] RISCV/dev/virtio/VirtIORng.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_VirtIOBlock.cc -> .os
[SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/python/_m5/param_VirtIORng.cc
[ SHCXX] RISCV/dev/virtio/VirtIO9P.py.cc -> .os
[SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/params/VirtIORng.hh
[ SHCXX] RISCV/python/_m5/param_VirtIORng.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/python/_m5/param_VirtIO9PBase.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/python/_m5/param_VirtIO9PProxy.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/params/VirtIO9PBase.hh
[SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/params/VirtIO9PProxy.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PBase.cc -> .os
[ SHCXX] RISCV/python/_m5/param_VirtIO9PProxy.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/python/_m5/param_VirtIO9PDiod.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/params/VirtIO9PDiod.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PDiod.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/python/_m5/param_VirtIO9PSocket.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/params/VirtIO9PSocket.hh
[ TRACING] -> RISCV/debug/VIO.hh
[ SHCXX] src/dev/virtio/base.cc -> RISCV/dev/virtio/base.os
[ SHCXX] RISCV/python/_m5/param_VirtIO9PSocket.cc -> .os
[ TRACING] -> RISCV/debug/VIOIface.hh
[ SHCXX] src/dev/virtio/pci.cc -> RISCV/dev/virtio/pci.os
[ TRACING] -> RISCV/debug/VIOConsole.hh
[ SHCXX] src/dev/virtio/console.cc -> RISCV/dev/virtio/console.os
[ TRACING] -> RISCV/debug/VIOBlock.hh
[ SHCXX] src/dev/virtio/block.cc -> RISCV/dev/virtio/block.os
[ TRACING] -> RISCV/debug/VIO9P.hh
[ TRACING] -> RISCV/debug/VIO9PData.hh
[ SHCXX] src/dev/virtio/fs9p.cc -> RISCV/dev/virtio/fs9p.os
[ TRACING] -> RISCV/debug/VIORng.hh
[ SHCXX] src/dev/virtio/rng.cc -> RISCV/dev/virtio/rng.os
[ TRACING] -> RISCV/debug/VIO.cc
[ SHCXX] RISCV/debug/VIO.cc -> .os
[ TRACING] -> RISCV/debug/VIORng.cc
[ SHCXX] RISCV/debug/VIORng.cc -> .os
[ TRACING] -> RISCV/debug/VIOIface.cc
[ TRACING] -> RISCV/debug/VIOConsole.cc
[ TRACING] -> RISCV/debug/VIOBlock.cc
[ SHCXX] RISCV/debug/VIOIface.cc -> .os
[ SHCXX] RISCV/debug/VIOConsole.cc -> .os
[ SHCXX] RISCV/debug/VIOBlock.cc -> .os
[ TRACING] -> RISCV/debug/VIO9P.cc
[ TRACING] -> RISCV/debug/VIO9PData.cc
[ SHCXX] RISCV/debug/VIO9P.cc -> .os
[ SHCXX] RISCV/debug/VIO9PData.cc -> .os
[ SHCXX] RISCV/python/m5/defines.py.cc -> .os
[ SHCXX] RISCV/python/m5/info.py.cc -> .os
[ SHCXX] src/base/date.cc -> RISCV/base/date.os
[ SHLINK] -> RISCV/libgem5_opt.so
scons: done building targets.
*** Summary of Warnings ***
Warning: Deprecated namespaces are not supported by this compiler.
Please make sure to check the mailing list for deprecation
announcements.
rm -f *.[do] libgem5.so
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder.o sst_responder.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o gem5.o gem5.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder_subcomponent.o sst_responder_subcomponent.cc
In file included from sst_responder.cc:27:
sst_responder.hh:50:10: fatal error: sim/sim_object.hh: No such file or directory
50 | #include <sim/sim_object.hh>
| ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: sst_responder.o] Error 1
make: *** Waiting for unfinished jobs....
In file included from sst_responder_subcomponent.cc:27:
sst_responder_subcomponent.hh:48:10: fatal error: sim/sim_object.hh: No such file or directory
48 | #include <sim/sim_object.hh>
| ^~~~~~~~~~~~~~~~~~~
compilation terminated.
In file included from gem5.cc:80:
gem5.hh:86:10: fatal error: sim/simulate.hh: No such file or directory
86 | #include <sim/simulate.hh>
| ^~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: gem5.o] Error 1
make: *** [<builtin>: sst_responder_subcomponent.o] Error 1
Build step 'Execute shell' marked build as failure
Archiving artifacts

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The following patch should fix this nightly bug: https://gem5-review.googlesource.com/c/public/gem5/+/69717 There was a small bug introduced where header files were not being added to the “build” directory. This broke the SST compilation as it uses the “build” directory as a include path. In addition, this patch will also fix the SST Makefile to not use the headers in the “build” directory. I think this is bad practice: https://gem5-review.googlesource.com/c/public/gem5/+/69718 -- Dr. Bobby R. Bruce Room 3050, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net > On Apr 10, 2023, at 3:34 PM, jenkins-no-reply--- via gem5-dev <gem5-dev@gem5.org> wrote: > > See <https://jenkins.gem5.org/job/nightly/571/display/redirect?page=changes> > > Changes: > > [gabe.black] base: Add support for unix domain sockets in ListenSocket. > > > ------------------------------------------ > [...truncated 4.44 MB...] > [SO Param] m5.objects.QemuFwCfg, QemuFwCfgMmio -> RISCV/python/_m5/param_QemuFwCfgMmio.cc > [ SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os > [ TRACING] -> RISCV/debug/QemuFwCfg.hh > [ TRACING] -> RISCV/debug/QemuFwCfgVerbose.hh > [ TRACING] -> RISCV/debug/QemuFwCfg.cc > [ SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os > [ TRACING] -> RISCV/debug/QemuFwCfgVerbose.cc > [ SHCXX] RISCV/debug/QemuFwCfg.cc -> .os > [ SHCXX] RISCV/dev/serial/Serial.py.cc -> .os > [ SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os > [SO Param] m5.objects.Serial, SerialDevice -> RISCV/python/_m5/param_SerialDevice.cc > [SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/python/_m5/param_SerialNullDevice.cc > [SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh > [SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/params/SerialNullDevice.hh > [ SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os > [SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc > [ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc > [ SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os > [ SHCXX] RISCV/dev/serial/Uart.py.cc -> .os > [ SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os > [ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh > [SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh > [ SHCXX] RISCV/enums/TerminalDump.cc -> .os > [ SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os > [SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc > [SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh > [ SHCXX] RISCV/python/_m5/param_Uart.cc -> .os > [SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc > [SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh > [ SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os > [SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc > [SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh > [ SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os > [ SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os > [ SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os > [ TRACING] -> RISCV/debug/Terminal.hh > [ TRACING] -> RISCV/debug/TerminalVerbose.hh > [ SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os > [ SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os > [ TRACING] -> RISCV/debug/Uart.hh > [ TRACING] -> RISCV/debug/Terminal.cc > [ SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os > [ SHCXX] RISCV/debug/Terminal.cc -> .os > [ TRACING] -> RISCV/debug/TerminalVerbose.cc > [ SHCXX] RISCV/debug/TerminalVerbose.cc -> .os > [ TRACING] -> RISCV/debug/Uart.cc > [ SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os > [ SHCXX] RISCV/debug/Uart.cc -> .os > [SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc > [SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc > [SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh > [SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh > [ SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os > [SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc > [SO Param] m5.objects.PciDevice, PciBarNone -> RISCV/python/_m5/param_PciBarNone.cc > [ SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os > [ SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os > [ SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os > [ SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os > [ SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os > [SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc > [ SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os > [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> RISCV/python/_m5/param_PciLegacyIoBar.cc > [ SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os > [SO Param] m5.objects.PciDevice, PciMemBar -> RISCV/python/_m5/param_PciMemBar.cc > [SO Param] m5.objects.PciDevice, PciMemUpperBar -> RISCV/python/_m5/param_PciMemUpperBar.cc > [ SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os > [SO Param] m5.objects.PciDevice, PciDevice -> RISCV/python/_m5/param_PciDevice.cc > [ TRACING] -> RISCV/debug/PciDevice.hh > [ TRACING] -> RISCV/debug/PciDevice.cc > [ SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os > [ SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os > [ SHCXX] RISCV/debug/PciDevice.cc -> .os > [ SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os > [ SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os > [SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc > [SO Param] m5.objects.PciHost, GenericPciHost -> RISCV/python/_m5/param_GenericPciHost.cc > [ TRACING] -> RISCV/debug/PciHost.hh > [ TRACING] -> RISCV/debug/PciHost.cc > [ SHCXX] src/dev/pci/host.cc -> RISCV/dev/pci/host.os > [ SHCXX] RISCV/debug/PciHost.cc -> .os > [ SHCXX] RISCV/python/_m5/param_PciHost.cc -> .os > [ SHCXX] RISCV/python/_m5/param_GenericPciHost.cc -> .os > [ SHCXX] RISCV/dev/pci/CopyEngine.py.cc -> .os > [SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/python/_m5/param_CopyEngine.cc > [ TRACING] -> RISCV/debug/DMACopyEngine.hh > [SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/params/CopyEngine.hh > [ TRACING] -> RISCV/debug/DMACopyEngine.cc > [ SHCXX] RISCV/debug/DMACopyEngine.cc -> .os > [ SHCXX] RISCV/python/_m5/param_CopyEngine.cc -> .os > [ SHCXX] src/dev/pci/copy_engine.cc -> RISCV/dev/pci/copy_engine.os > [ SHCXX] RISCV/dev/lupio/LupioBLK.py.cc -> .os > [SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/python/_m5/param_LupioBLK.cc > [SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/params/LupioBLK.hh > [ TRACING] -> RISCV/debug/LupioBLK.hh > [ SHCXX] RISCV/python/_m5/param_LupioBLK.cc -> .os > [ SHCXX] RISCV/dev/lupio/LupioIPI.py.cc -> .os > [SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/python/_m5/param_LupioIPI.cc > [ SHCXX] RISCV/dev/lupio/LupioPIC.py.cc -> .os > [SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/params/LupioIPI.hh > [ SHCXX] RISCV/python/_m5/param_LupioIPI.cc -> .os > [SO Param] m5.objects.LupioPIC, LupioPIC -> RISCV/python/_m5/param_LupioPIC.cc > [ SHCXX] RISCV/python/_m5/param_LupioPIC.cc -> .os > [ SHCXX] RISCV/dev/lupio/LupioRNG.py.cc -> .os > [SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/python/_m5/param_LupioRNG.cc > [ SHCXX] RISCV/dev/lupio/LupioRTC.py.cc -> .os > [SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/params/LupioRNG.hh > [ TRACING] -> RISCV/debug/LupioRNG.hh > [ SHCXX] RISCV/python/_m5/param_LupioRNG.cc -> .os > [SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/python/_m5/param_LupioRTC.cc > [SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/params/LupioRTC.hh > [ TRACING] -> RISCV/debug/LupioRTC.hh > [ SHCXX] RISCV/dev/lupio/LupioTMR.py.cc -> .os > [SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/python/_m5/param_LupioTMR.cc > [ SHCXX] RISCV/python/_m5/param_LupioRTC.cc -> .os > [ SHCXX] RISCV/dev/lupio/LupioTTY.py.cc -> .os > [SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/params/LupioTMR.hh > [ SHCXX] RISCV/python/_m5/param_LupioTMR.cc -> .os > [SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/python/_m5/param_LupioTTY.cc > [ SHCXX] RISCV/dev/lupio/LupioSYS.py.cc -> .os > [SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/python/_m5/param_LupioSYS.cc > [SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/params/LupioTTY.hh > [ TRACING] -> RISCV/debug/LupioBLK.cc > [ SHCXX] RISCV/debug/LupioBLK.cc -> .os > [SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/params/LupioSYS.hh > [ SHCXX] RISCV/python/_m5/param_LupioTTY.cc -> .os > [ TRACING] -> RISCV/debug/LupioSYS.hh > [ SHCXX] RISCV/python/_m5/param_LupioSYS.cc -> .os > [ TRACING] -> RISCV/debug/LupioIPI.cc > [ TRACING] -> RISCV/debug/LupioIPI.hh > [ SHCXX] RISCV/debug/LupioIPI.cc -> .os > [ TRACING] -> RISCV/debug/LupioPIC.cc > [ TRACING] -> RISCV/debug/LupioPIC.hh > [ SHCXX] RISCV/debug/LupioPIC.cc -> .os > [ TRACING] -> RISCV/debug/LupioRNG.cc > [ TRACING] -> RISCV/debug/LupioRTC.cc > [ SHCXX] RISCV/debug/LupioRNG.cc -> .os > [ SHCXX] RISCV/debug/LupioRTC.cc -> .os > [ TRACING] -> RISCV/debug/LupioTMR.cc > [ TRACING] -> RISCV/debug/LupioTMR.hh > [ SHCXX] RISCV/debug/LupioTMR.cc -> .os > [ TRACING] -> RISCV/debug/LupioTTY.cc > [ TRACING] -> RISCV/debug/LupioSYS.cc > [ TRACING] -> RISCV/debug/LupioTTY.hh > [ SHCXX] RISCV/debug/LupioSYS.cc -> .os > [ SHCXX] src/dev/lupio/lupio_blk.cc -> RISCV/dev/lupio/lupio_blk.os > [ SHCXX] src/dev/lupio/lupio_ipi.cc -> RISCV/dev/lupio/lupio_ipi.os > [ SHCXX] RISCV/debug/LupioTTY.cc -> .os > [ SHCXX] src/dev/lupio/lupio_pic.cc -> RISCV/dev/lupio/lupio_pic.os > [ SHCXX] src/dev/lupio/lupio_rng.cc -> RISCV/dev/lupio/lupio_rng.os > [ SHCXX] src/dev/lupio/lupio_rtc.cc -> RISCV/dev/lupio/lupio_rtc.os > [ SHCXX] src/dev/lupio/lupio_tmr.cc -> RISCV/dev/lupio/lupio_tmr.os > [ SHCXX] src/dev/lupio/lupio_tty.cc -> RISCV/dev/lupio/lupio_tty.os > [ SHCXX] src/dev/lupio/lupio_sys.cc -> RISCV/dev/lupio/lupio_sys.os > [ SHCXX] RISCV/dev/virtio/VirtIO.py.cc -> .os > [SO Param] m5.objects.VirtIO, VirtIODeviceBase -> RISCV/python/_m5/param_VirtIODeviceBase.cc > [ SHCXX] RISCV/python/_m5/param_VirtIODeviceBase.cc -> .os > [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/python/_m5/param_VirtIODummyDevice.cc > [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/params/VirtIODummyDevice.hh > [SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/python/_m5/param_PciVirtIO.cc > [ SHCXX] RISCV/dev/virtio/VirtIOConsole.py.cc -> .os > [ SHCXX] RISCV/python/_m5/param_VirtIODummyDevice.cc -> .os > [SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/params/PciVirtIO.hh > [ SHCXX] RISCV/python/_m5/param_PciVirtIO.cc -> .os > [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/python/_m5/param_VirtIOConsole.cc > [ SHCXX] RISCV/dev/virtio/VirtIOBlock.py.cc -> .os > [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/params/VirtIOConsole.hh > [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/python/_m5/param_VirtIOBlock.cc > [ SHCXX] RISCV/python/_m5/param_VirtIOConsole.cc -> .os > [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/params/VirtIOBlock.hh > [ SHCXX] RISCV/dev/virtio/VirtIORng.py.cc -> .os > [ SHCXX] RISCV/python/_m5/param_VirtIOBlock.cc -> .os > [SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/python/_m5/param_VirtIORng.cc > [ SHCXX] RISCV/dev/virtio/VirtIO9P.py.cc -> .os > [SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/params/VirtIORng.hh > [ SHCXX] RISCV/python/_m5/param_VirtIORng.cc -> .os > [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/python/_m5/param_VirtIO9PBase.cc > [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/python/_m5/param_VirtIO9PProxy.cc > [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/params/VirtIO9PBase.hh > [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/params/VirtIO9PProxy.hh > [ SHCXX] RISCV/python/_m5/param_VirtIO9PBase.cc -> .os > [ SHCXX] RISCV/python/_m5/param_VirtIO9PProxy.cc -> .os > [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/python/_m5/param_VirtIO9PDiod.cc > [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/params/VirtIO9PDiod.hh > [ SHCXX] RISCV/python/_m5/param_VirtIO9PDiod.cc -> .os > [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/python/_m5/param_VirtIO9PSocket.cc > [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/params/VirtIO9PSocket.hh > [ TRACING] -> RISCV/debug/VIO.hh > [ SHCXX] src/dev/virtio/base.cc -> RISCV/dev/virtio/base.os > [ SHCXX] RISCV/python/_m5/param_VirtIO9PSocket.cc -> .os > [ TRACING] -> RISCV/debug/VIOIface.hh > [ SHCXX] src/dev/virtio/pci.cc -> RISCV/dev/virtio/pci.os > [ TRACING] -> RISCV/debug/VIOConsole.hh > [ SHCXX] src/dev/virtio/console.cc -> RISCV/dev/virtio/console.os > [ TRACING] -> RISCV/debug/VIOBlock.hh > [ SHCXX] src/dev/virtio/block.cc -> RISCV/dev/virtio/block.os > [ TRACING] -> RISCV/debug/VIO9P.hh > [ TRACING] -> RISCV/debug/VIO9PData.hh > [ SHCXX] src/dev/virtio/fs9p.cc -> RISCV/dev/virtio/fs9p.os > [ TRACING] -> RISCV/debug/VIORng.hh > [ SHCXX] src/dev/virtio/rng.cc -> RISCV/dev/virtio/rng.os > [ TRACING] -> RISCV/debug/VIO.cc > [ SHCXX] RISCV/debug/VIO.cc -> .os > [ TRACING] -> RISCV/debug/VIORng.cc > [ SHCXX] RISCV/debug/VIORng.cc -> .os > [ TRACING] -> RISCV/debug/VIOIface.cc > [ TRACING] -> RISCV/debug/VIOConsole.cc > [ TRACING] -> RISCV/debug/VIOBlock.cc > [ SHCXX] RISCV/debug/VIOIface.cc -> .os > [ SHCXX] RISCV/debug/VIOConsole.cc -> .os > [ SHCXX] RISCV/debug/VIOBlock.cc -> .os > [ TRACING] -> RISCV/debug/VIO9P.cc > [ TRACING] -> RISCV/debug/VIO9PData.cc > [ SHCXX] RISCV/debug/VIO9P.cc -> .os > [ SHCXX] RISCV/debug/VIO9PData.cc -> .os > [ SHCXX] RISCV/python/m5/defines.py.cc -> .os > [ SHCXX] RISCV/python/m5/info.py.cc -> .os > [ SHCXX] src/base/date.cc -> RISCV/base/date.os > [ SHLINK] -> RISCV/libgem5_opt.so > scons: done building targets. > *** Summary of Warnings *** > Warning: Deprecated namespaces are not supported by this compiler. > Please make sure to check the mailing list for deprecation > announcements. > rm -f *.[do] libgem5.so > g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder.o sst_responder.cc > g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o gem5.o gem5.cc > g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder_subcomponent.o sst_responder_subcomponent.cc > In file included from sst_responder.cc:27: > sst_responder.hh:50:10: fatal error: sim/sim_object.hh: No such file or directory > 50 | #include <sim/sim_object.hh> > | ^~~~~~~~~~~~~~~~~~~ > compilation terminated. > make: *** [<builtin>: sst_responder.o] Error 1 > make: *** Waiting for unfinished jobs.... > In file included from sst_responder_subcomponent.cc:27: > sst_responder_subcomponent.hh:48:10: fatal error: sim/sim_object.hh: No such file or directory > 48 | #include <sim/sim_object.hh> > | ^~~~~~~~~~~~~~~~~~~ > compilation terminated. > In file included from gem5.cc:80: > gem5.hh:86:10: fatal error: sim/simulate.hh: No such file or directory > 86 | #include <sim/simulate.hh> > | ^~~~~~~~~~~~~~~~~ > compilation terminated. > make: *** [<builtin>: gem5.o] Error 1 > make: *** [<builtin>: sst_responder_subcomponent.o] Error 1 > Build step 'Execute shell' marked build as failure > Archiving artifacts > _______________________________________________ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-leave@gem5.org

jenkins-no-reply@gem5.org

Wed, Apr 12, 2023 10:25 PM

See https://jenkins.gem5.org/job/nightly/573/display/redirect?page=changes

Changes:

[gabe.black] mem: Use HostSocket in the SharedMemoryServer.

[rogerycchang] arch-riscv: Fix the address check of pmp

[rogerycchang] arch-riscv: Refactor the shouldCheckPMP function

[gabe.black] base,python: Add a param type for host sockets.

[gabe.black] base: Remove the now unused UnixSocketAddr class and associated code.

[gabe.black] arch,base,dev,sim: Convert objects to use the HostSocket param type.

[...truncated 4.44 MB...]
[SO Param] m5.objects.QemuFwCfg, QemuFwCfgMmio -> RISCV/python/_m5/param_QemuFwCfgMmio.cc
[ TRACING] -> RISCV/debug/QemuFwCfg.hh
[ TRACING] -> RISCV/debug/QemuFwCfgVerbose.hh
[ TRACING] -> RISCV/debug/QemuFwCfg.cc
[ TRACING] -> RISCV/debug/QemuFwCfgVerbose.cc
[ SHCXX] RISCV/dev/serial/Serial.py.cc -> .os
[ SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os
[ SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os
[SO Param] m5.objects.Serial, SerialDevice -> RISCV/python/_m5/param_SerialDevice.cc
[ SHCXX] RISCV/debug/QemuFwCfg.cc -> .os
[ SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os
[SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh
[SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/python/_m5/param_SerialNullDevice.cc
[ SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os
[ SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os
[SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc
[ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc
[ SHCXX] RISCV/dev/serial/Uart.py.cc -> .os
[SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/params/SerialNullDevice.hh
[ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh
[SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh
[ SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os
[ SHCXX] RISCV/enums/TerminalDump.cc -> .os
[ SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os
[SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc
[SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh
[ SHCXX] RISCV/python/_m5/param_Uart.cc -> .os
[SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc
[SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh
[ SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os
[SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc
[SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh
[ SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os
[ SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os
[ SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os
[ TRACING] -> RISCV/debug/Terminal.hh
[ TRACING] -> RISCV/debug/TerminalVerbose.hh
[ SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os
[ SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os
[ TRACING] -> RISCV/debug/Uart.hh
[ SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os
[ TRACING] -> RISCV/debug/Terminal.cc
[ TRACING] -> RISCV/debug/TerminalVerbose.cc
[ SHCXX] RISCV/debug/Terminal.cc -> .os
[ SHCXX] RISCV/debug/TerminalVerbose.cc -> .os
[ TRACING] -> RISCV/debug/Uart.cc
[ SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os
[ SHCXX] RISCV/debug/Uart.cc -> .os
[SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc
[SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc
[SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh
[SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh
[ SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os
[SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc
[SO Param] m5.objects.PciDevice, PciBarNone -> RISCV/python/_m5/param_PciBarNone.cc
[SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc
[ SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os
[ SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os
[ SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os
[ SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os
[SO Param] m5.objects.PciDevice, PciLegacyIoBar -> RISCV/python/_m5/param_PciLegacyIoBar.cc
[ SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciMemBar -> RISCV/python/_m5/param_PciMemBar.cc
[SO Param] m5.objects.PciDevice, PciMemUpperBar -> RISCV/python/_m5/param_PciMemUpperBar.cc
[ SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciDevice -> RISCV/python/_m5/param_PciDevice.cc
[ TRACING] -> RISCV/debug/PciDevice.hh
[ TRACING] -> RISCV/debug/PciDevice.cc
[ SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os
[ SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os
[ SHCXX] RISCV/debug/PciDevice.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os
[ SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os
[SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc
[ SHCXX] RISCV/python/_m5/param_PciHost.cc -> .os
[SO Param] m5.objects.PciHost, GenericPciHost -> RISCV/python/_m5/param_GenericPciHost.cc
[ TRACING] -> RISCV/debug/PciHost.hh
[ TRACING] -> RISCV/debug/PciHost.cc
[ SHCXX] src/dev/pci/host.cc -> RISCV/dev/pci/host.os
[ SHCXX] RISCV/debug/PciHost.cc -> .os
[ SHCXX] RISCV/python/_m5/param_GenericPciHost.cc -> .os
[ SHCXX] RISCV/dev/pci/CopyEngine.py.cc -> .os
[SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/python/_m5/param_CopyEngine.cc
[ TRACING] -> RISCV/debug/DMACopyEngine.hh
[SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/params/CopyEngine.hh
[ TRACING] -> RISCV/debug/DMACopyEngine.cc
[ SHCXX] RISCV/debug/DMACopyEngine.cc -> .os
[ SHCXX] RISCV/python/_m5/param_CopyEngine.cc -> .os
[ SHCXX] src/dev/pci/copy_engine.cc -> RISCV/dev/pci/copy_engine.os
[ SHCXX] RISCV/dev/lupio/LupioBLK.py.cc -> .os
[SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/python/_m5/param_LupioBLK.cc
[SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/params/LupioBLK.hh
[ TRACING] -> RISCV/debug/LupioBLK.hh
[ SHCXX] RISCV/python/_m5/param_LupioBLK.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioIPI.py.cc -> .os
[SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/python/_m5/param_LupioIPI.cc
[SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/params/LupioIPI.hh
[ SHCXX] RISCV/dev/lupio/LupioPIC.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioIPI.cc -> .os
[SO Param] m5.objects.LupioPIC, LupioPIC -> RISCV/python/_m5/param_LupioPIC.cc
[ SHCXX] RISCV/python/_m5/param_LupioPIC.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioRNG.py.cc -> .os
[SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/python/_m5/param_LupioRNG.cc
[SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/params/LupioRNG.hh
[ TRACING] -> RISCV/debug/LupioRNG.hh
[ SHCXX] RISCV/dev/lupio/LupioRTC.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioRNG.cc -> .os
[SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/python/_m5/param_LupioRTC.cc
[SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/params/LupioRTC.hh
[ TRACING] -> RISCV/debug/LupioRTC.hh
[ SHCXX] RISCV/dev/lupio/LupioTMR.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioRTC.cc -> .os
[SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/python/_m5/param_LupioTMR.cc
[SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/params/LupioTMR.hh
[ SHCXX] RISCV/dev/lupio/LupioTTY.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioTMR.cc -> .os
[SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/python/_m5/param_LupioTTY.cc
[SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/params/LupioTTY.hh
[ SHCXX] RISCV/dev/lupio/LupioSYS.py.cc -> .os
[SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/python/_m5/param_LupioSYS.cc
[ SHCXX] RISCV/python/_m5/param_LupioTTY.cc -> .os
[SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/params/LupioSYS.hh
[ TRACING] -> RISCV/debug/LupioSYS.hh
[ TRACING] -> RISCV/debug/LupioBLK.cc
[ SHCXX] RISCV/python/_m5/param_LupioSYS.cc -> .os
[ SHCXX] RISCV/debug/LupioBLK.cc -> .os
[ TRACING] -> RISCV/debug/LupioIPI.cc
[ TRACING] -> RISCV/debug/LupioIPI.hh
[ SHCXX] RISCV/debug/LupioIPI.cc -> .os
[ TRACING] -> RISCV/debug/LupioPIC.cc
[ TRACING] -> RISCV/debug/LupioPIC.hh
[ SHCXX] RISCV/debug/LupioPIC.cc -> .os
[ TRACING] -> RISCV/debug/LupioRNG.cc
[ SHCXX] RISCV/debug/LupioRNG.cc -> .os
[ TRACING] -> RISCV/debug/LupioRTC.cc
[ TRACING] -> RISCV/debug/LupioTMR.cc
[ SHCXX] RISCV/debug/LupioRTC.cc -> .os
[ TRACING] -> RISCV/debug/LupioTMR.hh
[ TRACING] -> RISCV/debug/LupioTTY.cc
[ SHCXX] RISCV/debug/LupioTMR.cc -> .os
[ TRACING] -> RISCV/debug/LupioTTY.hh
[ SHCXX] RISCV/debug/LupioTTY.cc -> .os
[ TRACING] -> RISCV/debug/LupioSYS.cc
[ SHCXX] src/dev/lupio/lupio_blk.cc -> RISCV/dev/lupio/lupio_blk.os
[ SHCXX] RISCV/debug/LupioSYS.cc -> .os
[ SHCXX] src/dev/lupio/lupio_ipi.cc -> RISCV/dev/lupio/lupio_ipi.os
[ SHCXX] src/dev/lupio/lupio_pic.cc -> RISCV/dev/lupio/lupio_pic.os
[ SHCXX] src/dev/lupio/lupio_rng.cc -> RISCV/dev/lupio/lupio_rng.os
[ SHCXX] src/dev/lupio/lupio_rtc.cc -> RISCV/dev/lupio/lupio_rtc.os
[ SHCXX] src/dev/lupio/lupio_tmr.cc -> RISCV/dev/lupio/lupio_tmr.os
[ SHCXX] src/dev/lupio/lupio_tty.cc -> RISCV/dev/lupio/lupio_tty.os
[ SHCXX] src/dev/lupio/lupio_sys.cc -> RISCV/dev/lupio/lupio_sys.os
[ SHCXX] RISCV/dev/virtio/VirtIO.py.cc -> .os
[SO Param] m5.objects.VirtIO, VirtIODeviceBase -> RISCV/python/_m5/param_VirtIODeviceBase.cc
[ SHCXX] RISCV/python/_m5/param_VirtIODeviceBase.cc -> .os
[SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/python/_m5/param_VirtIODummyDevice.cc
[SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/params/VirtIODummyDevice.hh
[SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/python/_m5/param_PciVirtIO.cc
[ SHCXX] RISCV/python/_m5/param_VirtIODummyDevice.cc -> .os
[ SHCXX] RISCV/dev/virtio/VirtIOConsole.py.cc -> .os
[SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/params/PciVirtIO.hh
[ SHCXX] RISCV/python/_m5/param_PciVirtIO.cc -> .os
[SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/python/_m5/param_VirtIOConsole.cc
[SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/params/VirtIOConsole.hh
[ SHCXX] RISCV/dev/virtio/VirtIOBlock.py.cc -> .os
[SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/python/_m5/param_VirtIOBlock.cc
[ SHCXX] RISCV/python/_m5/param_VirtIOConsole.cc -> .os
[SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/params/VirtIOBlock.hh
[ SHCXX] RISCV/dev/virtio/VirtIORng.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_VirtIOBlock.cc -> .os
[SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/python/_m5/param_VirtIORng.cc
[ SHCXX] RISCV/dev/virtio/VirtIO9P.py.cc -> .os
[SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/params/VirtIORng.hh
[ SHCXX] RISCV/python/_m5/param_VirtIORng.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/python/_m5/param_VirtIO9PBase.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/python/_m5/param_VirtIO9PProxy.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/params/VirtIO9PBase.hh
[SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/params/VirtIO9PProxy.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PBase.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/python/_m5/param_VirtIO9PDiod.cc
[ SHCXX] RISCV/python/_m5/param_VirtIO9PProxy.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/params/VirtIO9PDiod.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PDiod.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/python/_m5/param_VirtIO9PSocket.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/params/VirtIO9PSocket.hh
[ TRACING] -> RISCV/debug/VIO.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PSocket.cc -> .os
[ SHCXX] src/dev/virtio/base.cc -> RISCV/dev/virtio/base.os
[ TRACING] -> RISCV/debug/VIOIface.hh
[ SHCXX] src/dev/virtio/pci.cc -> RISCV/dev/virtio/pci.os
[ TRACING] -> RISCV/debug/VIOConsole.hh
[ SHCXX] src/dev/virtio/console.cc -> RISCV/dev/virtio/console.os
[ TRACING] -> RISCV/debug/VIOBlock.hh
[ SHCXX] src/dev/virtio/block.cc -> RISCV/dev/virtio/block.os
[ TRACING] -> RISCV/debug/VIO9P.hh
[ TRACING] -> RISCV/debug/VIO9PData.hh
[ SHCXX] src/dev/virtio/fs9p.cc -> RISCV/dev/virtio/fs9p.os
[ TRACING] -> RISCV/debug/VIORng.hh
[ SHCXX] src/dev/virtio/rng.cc -> RISCV/dev/virtio/rng.os
[ TRACING] -> RISCV/debug/VIO.cc
[ SHCXX] RISCV/debug/VIO.cc -> .os
[ TRACING] -> RISCV/debug/VIORng.cc
[ TRACING] -> RISCV/debug/VIOIface.cc
[ TRACING] -> RISCV/debug/VIOConsole.cc
[ SHCXX] RISCV/debug/VIORng.cc -> .os
[ SHCXX] RISCV/debug/VIOIface.cc -> .os
[ SHCXX] RISCV/debug/VIOConsole.cc -> .os
[ TRACING] -> RISCV/debug/VIOBlock.cc
[ TRACING] -> RISCV/debug/VIO9P.cc
[ SHCXX] RISCV/debug/VIOBlock.cc -> .os
[ SHCXX] RISCV/debug/VIO9P.cc -> .os
[ TRACING] -> RISCV/debug/VIO9PData.cc
[ SHCXX] RISCV/python/m5/defines.py.cc -> .os
[ SHCXX] RISCV/python/m5/info.py.cc -> .os
[ SHCXX] RISCV/debug/VIO9PData.cc -> .os
[ SHCXX] src/base/date.cc -> RISCV/base/date.os
[ SHLINK] -> RISCV/libgem5_opt.so
scons: done building targets.
*** Summary of Warnings ***
Warning: Deprecated namespaces are not supported by this compiler.
Please make sure to check the mailing list for deprecation
announcements.
rm -f *.[do] libgem5.so
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder.o sst_responder.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o gem5.o gem5.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder_subcomponent.o sst_responder_subcomponent.cc
In file included from sst_responder.cc:27:
sst_responder.hh:50:10: fatal error: sim/sim_object.hh: No such file or directory
50 | #include <sim/sim_object.hh>
| ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: sst_responder.o] Error 1
make: *** Waiting for unfinished jobs....
In file included from sst_responder_subcomponent.cc:27:
sst_responder_subcomponent.hh:48:10: fatal error: sim/sim_object.hh: No such file or directory
48 | #include <sim/sim_object.hh>
| ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: sst_responder_subcomponent.o] Error 1
In file included from gem5.cc:80:
gem5.hh:86:10: fatal error: sim/simulate.hh: No such file or directory
86 | #include <sim/simulate.hh>
| ^~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: gem5.o] Error 1
Build step 'Execute shell' marked build as failure
Archiving artifacts

See <https://jenkins.gem5.org/job/nightly/573/display/redirect?page=changes> Changes: [gabe.black] mem: Use HostSocket in the SharedMemoryServer. [rogerycchang] arch-riscv: Fix the address check of pmp [rogerycchang] arch-riscv: Refactor the shouldCheckPMP function [gabe.black] base,python: Add a param type for host sockets. [gabe.black] base: Remove the now unused UnixSocketAddr class and associated code. [gabe.black] arch,base,dev,sim: Convert objects to use the HostSocket param type. ------------------------------------------ [...truncated 4.44 MB...] [SO Param] m5.objects.QemuFwCfg, QemuFwCfgMmio -> RISCV/python/_m5/param_QemuFwCfgMmio.cc [ TRACING] -> RISCV/debug/QemuFwCfg.hh [ TRACING] -> RISCV/debug/QemuFwCfgVerbose.hh [ TRACING] -> RISCV/debug/QemuFwCfg.cc [ TRACING] -> RISCV/debug/QemuFwCfgVerbose.cc [ SHCXX] RISCV/dev/serial/Serial.py.cc -> .os [ SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os [ SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os [SO Param] m5.objects.Serial, SerialDevice -> RISCV/python/_m5/param_SerialDevice.cc [ SHCXX] RISCV/debug/QemuFwCfg.cc -> .os [ SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os [SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh [SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/python/_m5/param_SerialNullDevice.cc [ SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os [ SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os [SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc [ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc [ SHCXX] RISCV/dev/serial/Uart.py.cc -> .os [SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/params/SerialNullDevice.hh [ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh [SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh [ SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os [ SHCXX] RISCV/enums/TerminalDump.cc -> .os [ SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os [SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc [SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh [ SHCXX] RISCV/python/_m5/param_Uart.cc -> .os [SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc [SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh [ SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os [SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc [SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh [ SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os [ SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os [ SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os [ TRACING] -> RISCV/debug/Terminal.hh [ TRACING] -> RISCV/debug/TerminalVerbose.hh [ SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os [ SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os [ TRACING] -> RISCV/debug/Uart.hh [ SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os [ TRACING] -> RISCV/debug/Terminal.cc [ TRACING] -> RISCV/debug/TerminalVerbose.cc [ SHCXX] RISCV/debug/Terminal.cc -> .os [ SHCXX] RISCV/debug/TerminalVerbose.cc -> .os [ TRACING] -> RISCV/debug/Uart.cc [ SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os [ SHCXX] RISCV/debug/Uart.cc -> .os [SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc [SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc [SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh [SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh [ SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os [SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc [SO Param] m5.objects.PciDevice, PciBarNone -> RISCV/python/_m5/param_PciBarNone.cc [SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc [ SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os [ SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os [ SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os [ SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> RISCV/python/_m5/param_PciLegacyIoBar.cc [ SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os [SO Param] m5.objects.PciDevice, PciMemBar -> RISCV/python/_m5/param_PciMemBar.cc [SO Param] m5.objects.PciDevice, PciMemUpperBar -> RISCV/python/_m5/param_PciMemUpperBar.cc [ SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os [SO Param] m5.objects.PciDevice, PciDevice -> RISCV/python/_m5/param_PciDevice.cc [ TRACING] -> RISCV/debug/PciDevice.hh [ TRACING] -> RISCV/debug/PciDevice.cc [ SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os [ SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os [ SHCXX] RISCV/debug/PciDevice.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os [ SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os [SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc [ SHCXX] RISCV/python/_m5/param_PciHost.cc -> .os [SO Param] m5.objects.PciHost, GenericPciHost -> RISCV/python/_m5/param_GenericPciHost.cc [ TRACING] -> RISCV/debug/PciHost.hh [ TRACING] -> RISCV/debug/PciHost.cc [ SHCXX] src/dev/pci/host.cc -> RISCV/dev/pci/host.os [ SHCXX] RISCV/debug/PciHost.cc -> .os [ SHCXX] RISCV/python/_m5/param_GenericPciHost.cc -> .os [ SHCXX] RISCV/dev/pci/CopyEngine.py.cc -> .os [SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/python/_m5/param_CopyEngine.cc [ TRACING] -> RISCV/debug/DMACopyEngine.hh [SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/params/CopyEngine.hh [ TRACING] -> RISCV/debug/DMACopyEngine.cc [ SHCXX] RISCV/debug/DMACopyEngine.cc -> .os [ SHCXX] RISCV/python/_m5/param_CopyEngine.cc -> .os [ SHCXX] src/dev/pci/copy_engine.cc -> RISCV/dev/pci/copy_engine.os [ SHCXX] RISCV/dev/lupio/LupioBLK.py.cc -> .os [SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/python/_m5/param_LupioBLK.cc [SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/params/LupioBLK.hh [ TRACING] -> RISCV/debug/LupioBLK.hh [ SHCXX] RISCV/python/_m5/param_LupioBLK.cc -> .os [ SHCXX] RISCV/dev/lupio/LupioIPI.py.cc -> .os [SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/python/_m5/param_LupioIPI.cc [SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/params/LupioIPI.hh [ SHCXX] RISCV/dev/lupio/LupioPIC.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioIPI.cc -> .os [SO Param] m5.objects.LupioPIC, LupioPIC -> RISCV/python/_m5/param_LupioPIC.cc [ SHCXX] RISCV/python/_m5/param_LupioPIC.cc -> .os [ SHCXX] RISCV/dev/lupio/LupioRNG.py.cc -> .os [SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/python/_m5/param_LupioRNG.cc [SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/params/LupioRNG.hh [ TRACING] -> RISCV/debug/LupioRNG.hh [ SHCXX] RISCV/dev/lupio/LupioRTC.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioRNG.cc -> .os [SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/python/_m5/param_LupioRTC.cc [SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/params/LupioRTC.hh [ TRACING] -> RISCV/debug/LupioRTC.hh [ SHCXX] RISCV/dev/lupio/LupioTMR.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioRTC.cc -> .os [SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/python/_m5/param_LupioTMR.cc [SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/params/LupioTMR.hh [ SHCXX] RISCV/dev/lupio/LupioTTY.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioTMR.cc -> .os [SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/python/_m5/param_LupioTTY.cc [SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/params/LupioTTY.hh [ SHCXX] RISCV/dev/lupio/LupioSYS.py.cc -> .os [SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/python/_m5/param_LupioSYS.cc [ SHCXX] RISCV/python/_m5/param_LupioTTY.cc -> .os [SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/params/LupioSYS.hh [ TRACING] -> RISCV/debug/LupioSYS.hh [ TRACING] -> RISCV/debug/LupioBLK.cc [ SHCXX] RISCV/python/_m5/param_LupioSYS.cc -> .os [ SHCXX] RISCV/debug/LupioBLK.cc -> .os [ TRACING] -> RISCV/debug/LupioIPI.cc [ TRACING] -> RISCV/debug/LupioIPI.hh [ SHCXX] RISCV/debug/LupioIPI.cc -> .os [ TRACING] -> RISCV/debug/LupioPIC.cc [ TRACING] -> RISCV/debug/LupioPIC.hh [ SHCXX] RISCV/debug/LupioPIC.cc -> .os [ TRACING] -> RISCV/debug/LupioRNG.cc [ SHCXX] RISCV/debug/LupioRNG.cc -> .os [ TRACING] -> RISCV/debug/LupioRTC.cc [ TRACING] -> RISCV/debug/LupioTMR.cc [ SHCXX] RISCV/debug/LupioRTC.cc -> .os [ TRACING] -> RISCV/debug/LupioTMR.hh [ TRACING] -> RISCV/debug/LupioTTY.cc [ SHCXX] RISCV/debug/LupioTMR.cc -> .os [ TRACING] -> RISCV/debug/LupioTTY.hh [ SHCXX] RISCV/debug/LupioTTY.cc -> .os [ TRACING] -> RISCV/debug/LupioSYS.cc [ SHCXX] src/dev/lupio/lupio_blk.cc -> RISCV/dev/lupio/lupio_blk.os [ SHCXX] RISCV/debug/LupioSYS.cc -> .os [ SHCXX] src/dev/lupio/lupio_ipi.cc -> RISCV/dev/lupio/lupio_ipi.os [ SHCXX] src/dev/lupio/lupio_pic.cc -> RISCV/dev/lupio/lupio_pic.os [ SHCXX] src/dev/lupio/lupio_rng.cc -> RISCV/dev/lupio/lupio_rng.os [ SHCXX] src/dev/lupio/lupio_rtc.cc -> RISCV/dev/lupio/lupio_rtc.os [ SHCXX] src/dev/lupio/lupio_tmr.cc -> RISCV/dev/lupio/lupio_tmr.os [ SHCXX] src/dev/lupio/lupio_tty.cc -> RISCV/dev/lupio/lupio_tty.os [ SHCXX] src/dev/lupio/lupio_sys.cc -> RISCV/dev/lupio/lupio_sys.os [ SHCXX] RISCV/dev/virtio/VirtIO.py.cc -> .os [SO Param] m5.objects.VirtIO, VirtIODeviceBase -> RISCV/python/_m5/param_VirtIODeviceBase.cc [ SHCXX] RISCV/python/_m5/param_VirtIODeviceBase.cc -> .os [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/python/_m5/param_VirtIODummyDevice.cc [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/params/VirtIODummyDevice.hh [SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/python/_m5/param_PciVirtIO.cc [ SHCXX] RISCV/python/_m5/param_VirtIODummyDevice.cc -> .os [ SHCXX] RISCV/dev/virtio/VirtIOConsole.py.cc -> .os [SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/params/PciVirtIO.hh [ SHCXX] RISCV/python/_m5/param_PciVirtIO.cc -> .os [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/python/_m5/param_VirtIOConsole.cc [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/params/VirtIOConsole.hh [ SHCXX] RISCV/dev/virtio/VirtIOBlock.py.cc -> .os [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/python/_m5/param_VirtIOBlock.cc [ SHCXX] RISCV/python/_m5/param_VirtIOConsole.cc -> .os [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/params/VirtIOBlock.hh [ SHCXX] RISCV/dev/virtio/VirtIORng.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_VirtIOBlock.cc -> .os [SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/python/_m5/param_VirtIORng.cc [ SHCXX] RISCV/dev/virtio/VirtIO9P.py.cc -> .os [SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/params/VirtIORng.hh [ SHCXX] RISCV/python/_m5/param_VirtIORng.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/python/_m5/param_VirtIO9PBase.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/python/_m5/param_VirtIO9PProxy.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/params/VirtIO9PBase.hh [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/params/VirtIO9PProxy.hh [ SHCXX] RISCV/python/_m5/param_VirtIO9PBase.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/python/_m5/param_VirtIO9PDiod.cc [ SHCXX] RISCV/python/_m5/param_VirtIO9PProxy.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/params/VirtIO9PDiod.hh [ SHCXX] RISCV/python/_m5/param_VirtIO9PDiod.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/python/_m5/param_VirtIO9PSocket.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/params/VirtIO9PSocket.hh [ TRACING] -> RISCV/debug/VIO.hh [ SHCXX] RISCV/python/_m5/param_VirtIO9PSocket.cc -> .os [ SHCXX] src/dev/virtio/base.cc -> RISCV/dev/virtio/base.os [ TRACING] -> RISCV/debug/VIOIface.hh [ SHCXX] src/dev/virtio/pci.cc -> RISCV/dev/virtio/pci.os [ TRACING] -> RISCV/debug/VIOConsole.hh [ SHCXX] src/dev/virtio/console.cc -> RISCV/dev/virtio/console.os [ TRACING] -> RISCV/debug/VIOBlock.hh [ SHCXX] src/dev/virtio/block.cc -> RISCV/dev/virtio/block.os [ TRACING] -> RISCV/debug/VIO9P.hh [ TRACING] -> RISCV/debug/VIO9PData.hh [ SHCXX] src/dev/virtio/fs9p.cc -> RISCV/dev/virtio/fs9p.os [ TRACING] -> RISCV/debug/VIORng.hh [ SHCXX] src/dev/virtio/rng.cc -> RISCV/dev/virtio/rng.os [ TRACING] -> RISCV/debug/VIO.cc [ SHCXX] RISCV/debug/VIO.cc -> .os [ TRACING] -> RISCV/debug/VIORng.cc [ TRACING] -> RISCV/debug/VIOIface.cc [ TRACING] -> RISCV/debug/VIOConsole.cc [ SHCXX] RISCV/debug/VIORng.cc -> .os [ SHCXX] RISCV/debug/VIOIface.cc -> .os [ SHCXX] RISCV/debug/VIOConsole.cc -> .os [ TRACING] -> RISCV/debug/VIOBlock.cc [ TRACING] -> RISCV/debug/VIO9P.cc [ SHCXX] RISCV/debug/VIOBlock.cc -> .os [ SHCXX] RISCV/debug/VIO9P.cc -> .os [ TRACING] -> RISCV/debug/VIO9PData.cc [ SHCXX] RISCV/python/m5/defines.py.cc -> .os [ SHCXX] RISCV/python/m5/info.py.cc -> .os [ SHCXX] RISCV/debug/VIO9PData.cc -> .os [ SHCXX] src/base/date.cc -> RISCV/base/date.os [ SHLINK] -> RISCV/libgem5_opt.so scons: done building targets. *** Summary of Warnings *** Warning: Deprecated namespaces are not supported by this compiler. Please make sure to check the mailing list for deprecation announcements. rm -f *.[do] libgem5.so g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder.o sst_responder.cc g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o gem5.o gem5.cc g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder_subcomponent.o sst_responder_subcomponent.cc In file included from sst_responder.cc:27: sst_responder.hh:50:10: fatal error: sim/sim_object.hh: No such file or directory 50 | #include <sim/sim_object.hh> | ^~~~~~~~~~~~~~~~~~~ compilation terminated. make: *** [<builtin>: sst_responder.o] Error 1 make: *** Waiting for unfinished jobs.... In file included from sst_responder_subcomponent.cc:27: sst_responder_subcomponent.hh:48:10: fatal error: sim/sim_object.hh: No such file or directory 48 | #include <sim/sim_object.hh> | ^~~~~~~~~~~~~~~~~~~ compilation terminated. make: *** [<builtin>: sst_responder_subcomponent.o] Error 1 In file included from gem5.cc:80: gem5.hh:86:10: fatal error: sim/simulate.hh: No such file or directory 86 | #include <sim/simulate.hh> | ^~~~~~~~~~~~~~~~~ compilation terminated. make: *** [<builtin>: gem5.o] Error 1 Build step 'Execute shell' marked build as failure Archiving artifacts

jenkins-no-reply@gem5.org

Thu, Apr 13, 2023 10:18 PM

See https://jenkins.gem5.org/job/nightly/574/display/redirect?page=changes

Changes:

[gabe.black] base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

[rogerycchang] arch-riscv: Insert symbol table of bootloader into debug symbol table

[...truncated 4.44 MB...]
[ SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os
[ TRACING] -> RISCV/debug/QemuFwCfg.hh
[ SHCXX] RISCV/python/_m5/param_QemuFwCfgIo.cc -> .os
[ TRACING] -> RISCV/debug/QemuFwCfgVerbose.hh
[ TRACING] -> RISCV/debug/QemuFwCfg.cc
[ TRACING] -> RISCV/debug/QemuFwCfgVerbose.cc
[ SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os
[ SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os
[ SHCXX] RISCV/debug/QemuFwCfg.cc -> .os
[ SHCXX] RISCV/dev/serial/Serial.py.cc -> .os
[SO Param] m5.objects.Serial, SerialDevice -> RISCV/python/_m5/param_SerialDevice.cc
[SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh
[SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/python/_m5/param_SerialNullDevice.cc
[ SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os
[SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc
[ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc
[ SHCXX] RISCV/dev/serial/Uart.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os
[SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/params/SerialNullDevice.hh
[ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh
[SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh
[ SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os
[ SHCXX] RISCV/enums/TerminalDump.cc -> .os
[ SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os
[SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc
[SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh
[ SHCXX] RISCV/python/_m5/param_Uart.cc -> .os
[SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc
[SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh
[SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc
[ SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os
[SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh
[ SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os
[ SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os
[ SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os
[ TRACING] -> RISCV/debug/Terminal.hh
[ TRACING] -> RISCV/debug/TerminalVerbose.hh
[ SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os
[ SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os
[ TRACING] -> RISCV/debug/Uart.hh
[ SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os
[ TRACING] -> RISCV/debug/Terminal.cc
[ SHCXX] RISCV/debug/Terminal.cc -> .os
[ TRACING] -> RISCV/debug/TerminalVerbose.cc
[ TRACING] -> RISCV/debug/Uart.cc
[ SHCXX] RISCV/debug/TerminalVerbose.cc -> .os
[ SHCXX] RISCV/debug/Uart.cc -> .os
[ SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os
[SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc
[SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc
[SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh
[SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh
[ SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os
[SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc
[SO Param] m5.objects.PciDevice, PciBarNone -> RISCV/python/_m5/param_PciBarNone.cc
[SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc
[ SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os
[ SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os
[ SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os
[SO Param] m5.objects.PciDevice, PciLegacyIoBar -> RISCV/python/_m5/param_PciLegacyIoBar.cc
[ SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciMemBar -> RISCV/python/_m5/param_PciMemBar.cc
[SO Param] m5.objects.PciDevice, PciMemUpperBar -> RISCV/python/_m5/param_PciMemUpperBar.cc
[ SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os
[SO Param] m5.objects.PciDevice, PciDevice -> RISCV/python/_m5/param_PciDevice.cc
[ TRACING] -> RISCV/debug/PciDevice.hh
[ TRACING] -> RISCV/debug/PciDevice.cc
[ SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os
[ SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os
[ SHCXX] RISCV/debug/PciDevice.cc -> .os
[ SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os
[ SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os
[SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc
[SO Param] m5.objects.PciHost, GenericPciHost -> RISCV/python/_m5/param_GenericPciHost.cc
[ SHCXX] RISCV/python/_m5/param_PciHost.cc -> .os
[ TRACING] -> RISCV/debug/PciHost.hh
[ SHCXX] src/dev/pci/host.cc -> RISCV/dev/pci/host.os
[ SHCXX] RISCV/python/_m5/param_GenericPciHost.cc -> .os
[ TRACING] -> RISCV/debug/PciHost.cc
[ SHCXX] RISCV/debug/PciHost.cc -> .os
[ SHCXX] RISCV/dev/pci/CopyEngine.py.cc -> .os
[SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/python/_m5/param_CopyEngine.cc
[ TRACING] -> RISCV/debug/DMACopyEngine.hh
[SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/params/CopyEngine.hh
[ TRACING] -> RISCV/debug/DMACopyEngine.cc
[ SHCXX] RISCV/debug/DMACopyEngine.cc -> .os
[ SHCXX] src/dev/pci/copy_engine.cc -> RISCV/dev/pci/copy_engine.os
[ SHCXX] RISCV/python/_m5/param_CopyEngine.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioBLK.py.cc -> .os
[SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/python/_m5/param_LupioBLK.cc
[SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/params/LupioBLK.hh
[ TRACING] -> RISCV/debug/LupioBLK.hh
[ SHCXX] RISCV/python/_m5/param_LupioBLK.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioIPI.py.cc -> .os
[SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/python/_m5/param_LupioIPI.cc
[SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/params/LupioIPI.hh
[ SHCXX] RISCV/dev/lupio/LupioPIC.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioIPI.cc -> .os
[SO Param] m5.objects.LupioPIC, LupioPIC -> RISCV/python/_m5/param_LupioPIC.cc
[ SHCXX] RISCV/python/_m5/param_LupioPIC.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioRNG.py.cc -> .os
[SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/python/_m5/param_LupioRNG.cc
[SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/params/LupioRNG.hh
[ TRACING] -> RISCV/debug/LupioRNG.hh
[ SHCXX] RISCV/dev/lupio/LupioRTC.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioRNG.cc -> .os
[SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/python/_m5/param_LupioRTC.cc
[SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/params/LupioRTC.hh
[ TRACING] -> RISCV/debug/LupioRTC.hh
[ SHCXX] RISCV/python/_m5/param_LupioRTC.cc -> .os
[ SHCXX] RISCV/dev/lupio/LupioTMR.py.cc -> .os
[SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/python/_m5/param_LupioTMR.cc
[ SHCXX] RISCV/dev/lupio/LupioTTY.py.cc -> .os
[SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/params/LupioTMR.hh
[SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/python/_m5/param_LupioTTY.cc
[ SHCXX] RISCV/dev/lupio/LupioSYS.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_LupioTMR.cc -> .os
[SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/python/_m5/param_LupioSYS.cc
[SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/params/LupioTTY.hh
[SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/params/LupioSYS.hh
[ SHCXX] RISCV/python/_m5/param_LupioTTY.cc -> .os
[ TRACING] -> RISCV/debug/LupioSYS.hh
[ TRACING] -> RISCV/debug/LupioBLK.cc
[ SHCXX] RISCV/python/_m5/param_LupioSYS.cc -> .os
[ SHCXX] RISCV/debug/LupioBLK.cc -> .os
[ TRACING] -> RISCV/debug/LupioIPI.cc
[ TRACING] -> RISCV/debug/LupioIPI.hh
[ SHCXX] RISCV/debug/LupioIPI.cc -> .os
[ TRACING] -> RISCV/debug/LupioPIC.cc
[ TRACING] -> RISCV/debug/LupioPIC.hh
[ SHCXX] RISCV/debug/LupioPIC.cc -> .os
[ TRACING] -> RISCV/debug/LupioRNG.cc
[ SHCXX] RISCV/debug/LupioRNG.cc -> .os
[ TRACING] -> RISCV/debug/LupioRTC.cc
[ SHCXX] RISCV/debug/LupioRTC.cc -> .os
[ TRACING] -> RISCV/debug/LupioTMR.cc
[ TRACING] -> RISCV/debug/LupioTTY.cc
[ TRACING] -> RISCV/debug/LupioTMR.hh
[ TRACING] -> RISCV/debug/LupioTTY.hh
[ TRACING] -> RISCV/debug/LupioSYS.cc
[ SHCXX] RISCV/debug/LupioTMR.cc -> .os
[ SHCXX] src/dev/lupio/lupio_blk.cc -> RISCV/dev/lupio/lupio_blk.os
[ SHCXX] RISCV/debug/LupioSYS.cc -> .os
[ SHCXX] RISCV/debug/LupioTTY.cc -> .os
[ SHCXX] src/dev/lupio/lupio_ipi.cc -> RISCV/dev/lupio/lupio_ipi.os
[ SHCXX] src/dev/lupio/lupio_pic.cc -> RISCV/dev/lupio/lupio_pic.os
[ SHCXX] src/dev/lupio/lupio_rng.cc -> RISCV/dev/lupio/lupio_rng.os
[ SHCXX] src/dev/lupio/lupio_rtc.cc -> RISCV/dev/lupio/lupio_rtc.os
[ SHCXX] src/dev/lupio/lupio_tmr.cc -> RISCV/dev/lupio/lupio_tmr.os
[ SHCXX] src/dev/lupio/lupio_tty.cc -> RISCV/dev/lupio/lupio_tty.os
[ SHCXX] src/dev/lupio/lupio_sys.cc -> RISCV/dev/lupio/lupio_sys.os
[ SHCXX] RISCV/dev/virtio/VirtIO.py.cc -> .os
[SO Param] m5.objects.VirtIO, VirtIODeviceBase -> RISCV/python/_m5/param_VirtIODeviceBase.cc
[SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/python/_m5/param_VirtIODummyDevice.cc
[ SHCXX] RISCV/python/_m5/param_VirtIODeviceBase.cc -> .os
[SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/params/VirtIODummyDevice.hh
[ SHCXX] RISCV/python/_m5/param_VirtIODummyDevice.cc -> .os
[SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/python/_m5/param_PciVirtIO.cc
[SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/params/PciVirtIO.hh
[ SHCXX] RISCV/python/_m5/param_PciVirtIO.cc -> .os
[ SHCXX] RISCV/dev/virtio/VirtIOConsole.py.cc -> .os
[SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/python/_m5/param_VirtIOConsole.cc
[ SHCXX] RISCV/dev/virtio/VirtIOBlock.py.cc -> .os
[SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/python/_m5/param_VirtIOBlock.cc
[SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/params/VirtIOConsole.hh
[SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/params/VirtIOBlock.hh
[ SHCXX] RISCV/dev/virtio/VirtIORng.py.cc -> .os
[ SHCXX] RISCV/python/_m5/param_VirtIOConsole.cc -> .os
[SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/python/_m5/param_VirtIORng.cc
[ SHCXX] RISCV/python/_m5/param_VirtIOBlock.cc -> .os
[ SHCXX] RISCV/dev/virtio/VirtIO9P.py.cc -> .os
[SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/params/VirtIORng.hh
[ SHCXX] RISCV/python/_m5/param_VirtIORng.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/python/_m5/param_VirtIO9PBase.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/python/_m5/param_VirtIO9PProxy.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/params/VirtIO9PBase.hh
[SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/params/VirtIO9PProxy.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PBase.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/python/_m5/param_VirtIO9PDiod.cc
[ SHCXX] RISCV/python/_m5/param_VirtIO9PProxy.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/params/VirtIO9PDiod.hh
[ SHCXX] RISCV/python/_m5/param_VirtIO9PDiod.cc -> .os
[SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/python/_m5/param_VirtIO9PSocket.cc
[SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/params/VirtIO9PSocket.hh
[ TRACING] -> RISCV/debug/VIO.hh
[ SHCXX] src/dev/virtio/base.cc -> RISCV/dev/virtio/base.os
[ SHCXX] RISCV/python/_m5/param_VirtIO9PSocket.cc -> .os
[ TRACING] -> RISCV/debug/VIOIface.hh
[ SHCXX] src/dev/virtio/pci.cc -> RISCV/dev/virtio/pci.os
[ TRACING] -> RISCV/debug/VIOConsole.hh
[ SHCXX] src/dev/virtio/console.cc -> RISCV/dev/virtio/console.os
[ TRACING] -> RISCV/debug/VIOBlock.hh
[ SHCXX] src/dev/virtio/block.cc -> RISCV/dev/virtio/block.os
[ TRACING] -> RISCV/debug/VIO9P.hh
[ TRACING] -> RISCV/debug/VIO9PData.hh
[ SHCXX] src/dev/virtio/fs9p.cc -> RISCV/dev/virtio/fs9p.os
[ TRACING] -> RISCV/debug/VIORng.hh
[ SHCXX] src/dev/virtio/rng.cc -> RISCV/dev/virtio/rng.os
[ TRACING] -> RISCV/debug/VIO.cc
[ TRACING] -> RISCV/debug/VIORng.cc
[ SHCXX] RISCV/debug/VIO.cc -> .os
[ SHCXX] RISCV/debug/VIORng.cc -> .os
[ TRACING] -> RISCV/debug/VIOIface.cc
[ SHCXX] RISCV/debug/VIOIface.cc -> .os
[ TRACING] -> RISCV/debug/VIOConsole.cc
[ TRACING] -> RISCV/debug/VIOBlock.cc
[ SHCXX] RISCV/debug/VIOConsole.cc -> .os
[ SHCXX] RISCV/debug/VIOBlock.cc -> .os
[ TRACING] -> RISCV/debug/VIO9P.cc
[ TRACING] -> RISCV/debug/VIO9PData.cc
[ SHCXX] RISCV/debug/VIO9P.cc -> .os
[ SHCXX] RISCV/python/m5/defines.py.cc -> .os
[ SHCXX] RISCV/debug/VIO9PData.cc -> .os
[ SHCXX] RISCV/python/m5/info.py.cc -> .os
[ SHCXX] src/base/date.cc -> RISCV/base/date.os
[ SHLINK] -> RISCV/libgem5_opt.so
scons: done building targets.
*** Summary of Warnings ***
Warning: Deprecated namespaces are not supported by this compiler.
Please make sure to check the mailing list for deprecation
announcements.
rm -f *.[do] libgem5.so
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder.o sst_responder.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o gem5.o gem5.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder_subcomponent.o sst_responder_subcomponent.cc
In file included from sst_responder.cc:27:
sst_responder.hh:50:10: fatal error: sim/sim_object.hh: No such file or directory
50 | #include <sim/sim_object.hh>
| ^~~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: sst_responder.o] Error 1
make: *** Waiting for unfinished jobs....
In file included from sst_responder_subcomponent.cc:27:
sst_responder_subcomponent.hh:48:10: fatal error: sim/sim_object.hh: No such file or directory
48 | #include <sim/sim_object.hh>
| ^~~~~~~~~~~~~~~~~~~
compilation terminated.
In file included from gem5.cc:80:
gem5.hh:86:10: fatal error: sim/simulate.hh: No such file or directory
86 | #include <sim/simulate.hh>
| ^~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [<builtin>: sst_responder_subcomponent.o] Error 1
make: *** [<builtin>: gem5.o] Error 1
Build step 'Execute shell' marked build as failure
Archiving artifacts

See <https://jenkins.gem5.org/job/nightly/574/display/redirect?page=changes> Changes: [gabe.black] base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path. [rogerycchang] arch-riscv: Insert symbol table of bootloader into debug symbol table ------------------------------------------ [...truncated 4.44 MB...] [ SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os [ TRACING] -> RISCV/debug/QemuFwCfg.hh [ SHCXX] RISCV/python/_m5/param_QemuFwCfgIo.cc -> .os [ TRACING] -> RISCV/debug/QemuFwCfgVerbose.hh [ TRACING] -> RISCV/debug/QemuFwCfg.cc [ TRACING] -> RISCV/debug/QemuFwCfgVerbose.cc [ SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os [ SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os [ SHCXX] RISCV/debug/QemuFwCfg.cc -> .os [ SHCXX] RISCV/dev/serial/Serial.py.cc -> .os [SO Param] m5.objects.Serial, SerialDevice -> RISCV/python/_m5/param_SerialDevice.cc [SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh [SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/python/_m5/param_SerialNullDevice.cc [ SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os [SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc [ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc [ SHCXX] RISCV/dev/serial/Uart.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os [SO Param] m5.objects.Serial, SerialNullDevice -> RISCV/params/SerialNullDevice.hh [ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh [SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh [ SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os [ SHCXX] RISCV/enums/TerminalDump.cc -> .os [ SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os [SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc [SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh [ SHCXX] RISCV/python/_m5/param_Uart.cc -> .os [SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc [SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh [SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc [ SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os [SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh [ SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os [ SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os [ SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os [ TRACING] -> RISCV/debug/Terminal.hh [ TRACING] -> RISCV/debug/TerminalVerbose.hh [ SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os [ SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os [ TRACING] -> RISCV/debug/Uart.hh [ SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os [ TRACING] -> RISCV/debug/Terminal.cc [ SHCXX] RISCV/debug/Terminal.cc -> .os [ TRACING] -> RISCV/debug/TerminalVerbose.cc [ TRACING] -> RISCV/debug/Uart.cc [ SHCXX] RISCV/debug/TerminalVerbose.cc -> .os [ SHCXX] RISCV/debug/Uart.cc -> .os [ SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os [SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc [SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc [SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh [SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh [ SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os [SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc [SO Param] m5.objects.PciDevice, PciBarNone -> RISCV/python/_m5/param_PciBarNone.cc [SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc [ SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os [ SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os [ SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> RISCV/python/_m5/param_PciLegacyIoBar.cc [ SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os [SO Param] m5.objects.PciDevice, PciMemBar -> RISCV/python/_m5/param_PciMemBar.cc [SO Param] m5.objects.PciDevice, PciMemUpperBar -> RISCV/python/_m5/param_PciMemUpperBar.cc [ SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os [SO Param] m5.objects.PciDevice, PciDevice -> RISCV/python/_m5/param_PciDevice.cc [ TRACING] -> RISCV/debug/PciDevice.hh [ TRACING] -> RISCV/debug/PciDevice.cc [ SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os [ SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os [ SHCXX] RISCV/debug/PciDevice.cc -> .os [ SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os [ SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os [SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc [SO Param] m5.objects.PciHost, GenericPciHost -> RISCV/python/_m5/param_GenericPciHost.cc [ SHCXX] RISCV/python/_m5/param_PciHost.cc -> .os [ TRACING] -> RISCV/debug/PciHost.hh [ SHCXX] src/dev/pci/host.cc -> RISCV/dev/pci/host.os [ SHCXX] RISCV/python/_m5/param_GenericPciHost.cc -> .os [ TRACING] -> RISCV/debug/PciHost.cc [ SHCXX] RISCV/debug/PciHost.cc -> .os [ SHCXX] RISCV/dev/pci/CopyEngine.py.cc -> .os [SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/python/_m5/param_CopyEngine.cc [ TRACING] -> RISCV/debug/DMACopyEngine.hh [SO Param] m5.objects.CopyEngine, CopyEngine -> RISCV/params/CopyEngine.hh [ TRACING] -> RISCV/debug/DMACopyEngine.cc [ SHCXX] RISCV/debug/DMACopyEngine.cc -> .os [ SHCXX] src/dev/pci/copy_engine.cc -> RISCV/dev/pci/copy_engine.os [ SHCXX] RISCV/python/_m5/param_CopyEngine.cc -> .os [ SHCXX] RISCV/dev/lupio/LupioBLK.py.cc -> .os [SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/python/_m5/param_LupioBLK.cc [SO Param] m5.objects.LupioBLK, LupioBLK -> RISCV/params/LupioBLK.hh [ TRACING] -> RISCV/debug/LupioBLK.hh [ SHCXX] RISCV/python/_m5/param_LupioBLK.cc -> .os [ SHCXX] RISCV/dev/lupio/LupioIPI.py.cc -> .os [SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/python/_m5/param_LupioIPI.cc [SO Param] m5.objects.LupioIPI, LupioIPI -> RISCV/params/LupioIPI.hh [ SHCXX] RISCV/dev/lupio/LupioPIC.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioIPI.cc -> .os [SO Param] m5.objects.LupioPIC, LupioPIC -> RISCV/python/_m5/param_LupioPIC.cc [ SHCXX] RISCV/python/_m5/param_LupioPIC.cc -> .os [ SHCXX] RISCV/dev/lupio/LupioRNG.py.cc -> .os [SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/python/_m5/param_LupioRNG.cc [SO Param] m5.objects.LupioRNG, LupioRNG -> RISCV/params/LupioRNG.hh [ TRACING] -> RISCV/debug/LupioRNG.hh [ SHCXX] RISCV/dev/lupio/LupioRTC.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioRNG.cc -> .os [SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/python/_m5/param_LupioRTC.cc [SO Param] m5.objects.LupioRTC, LupioRTC -> RISCV/params/LupioRTC.hh [ TRACING] -> RISCV/debug/LupioRTC.hh [ SHCXX] RISCV/python/_m5/param_LupioRTC.cc -> .os [ SHCXX] RISCV/dev/lupio/LupioTMR.py.cc -> .os [SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/python/_m5/param_LupioTMR.cc [ SHCXX] RISCV/dev/lupio/LupioTTY.py.cc -> .os [SO Param] m5.objects.LupioTMR, LupioTMR -> RISCV/params/LupioTMR.hh [SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/python/_m5/param_LupioTTY.cc [ SHCXX] RISCV/dev/lupio/LupioSYS.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_LupioTMR.cc -> .os [SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/python/_m5/param_LupioSYS.cc [SO Param] m5.objects.LupioTTY, LupioTTY -> RISCV/params/LupioTTY.hh [SO Param] m5.objects.LupioSYS, LupioSYS -> RISCV/params/LupioSYS.hh [ SHCXX] RISCV/python/_m5/param_LupioTTY.cc -> .os [ TRACING] -> RISCV/debug/LupioSYS.hh [ TRACING] -> RISCV/debug/LupioBLK.cc [ SHCXX] RISCV/python/_m5/param_LupioSYS.cc -> .os [ SHCXX] RISCV/debug/LupioBLK.cc -> .os [ TRACING] -> RISCV/debug/LupioIPI.cc [ TRACING] -> RISCV/debug/LupioIPI.hh [ SHCXX] RISCV/debug/LupioIPI.cc -> .os [ TRACING] -> RISCV/debug/LupioPIC.cc [ TRACING] -> RISCV/debug/LupioPIC.hh [ SHCXX] RISCV/debug/LupioPIC.cc -> .os [ TRACING] -> RISCV/debug/LupioRNG.cc [ SHCXX] RISCV/debug/LupioRNG.cc -> .os [ TRACING] -> RISCV/debug/LupioRTC.cc [ SHCXX] RISCV/debug/LupioRTC.cc -> .os [ TRACING] -> RISCV/debug/LupioTMR.cc [ TRACING] -> RISCV/debug/LupioTTY.cc [ TRACING] -> RISCV/debug/LupioTMR.hh [ TRACING] -> RISCV/debug/LupioTTY.hh [ TRACING] -> RISCV/debug/LupioSYS.cc [ SHCXX] RISCV/debug/LupioTMR.cc -> .os [ SHCXX] src/dev/lupio/lupio_blk.cc -> RISCV/dev/lupio/lupio_blk.os [ SHCXX] RISCV/debug/LupioSYS.cc -> .os [ SHCXX] RISCV/debug/LupioTTY.cc -> .os [ SHCXX] src/dev/lupio/lupio_ipi.cc -> RISCV/dev/lupio/lupio_ipi.os [ SHCXX] src/dev/lupio/lupio_pic.cc -> RISCV/dev/lupio/lupio_pic.os [ SHCXX] src/dev/lupio/lupio_rng.cc -> RISCV/dev/lupio/lupio_rng.os [ SHCXX] src/dev/lupio/lupio_rtc.cc -> RISCV/dev/lupio/lupio_rtc.os [ SHCXX] src/dev/lupio/lupio_tmr.cc -> RISCV/dev/lupio/lupio_tmr.os [ SHCXX] src/dev/lupio/lupio_tty.cc -> RISCV/dev/lupio/lupio_tty.os [ SHCXX] src/dev/lupio/lupio_sys.cc -> RISCV/dev/lupio/lupio_sys.os [ SHCXX] RISCV/dev/virtio/VirtIO.py.cc -> .os [SO Param] m5.objects.VirtIO, VirtIODeviceBase -> RISCV/python/_m5/param_VirtIODeviceBase.cc [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/python/_m5/param_VirtIODummyDevice.cc [ SHCXX] RISCV/python/_m5/param_VirtIODeviceBase.cc -> .os [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> RISCV/params/VirtIODummyDevice.hh [ SHCXX] RISCV/python/_m5/param_VirtIODummyDevice.cc -> .os [SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/python/_m5/param_PciVirtIO.cc [SO Param] m5.objects.VirtIO, PciVirtIO -> RISCV/params/PciVirtIO.hh [ SHCXX] RISCV/python/_m5/param_PciVirtIO.cc -> .os [ SHCXX] RISCV/dev/virtio/VirtIOConsole.py.cc -> .os [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/python/_m5/param_VirtIOConsole.cc [ SHCXX] RISCV/dev/virtio/VirtIOBlock.py.cc -> .os [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/python/_m5/param_VirtIOBlock.cc [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> RISCV/params/VirtIOConsole.hh [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> RISCV/params/VirtIOBlock.hh [ SHCXX] RISCV/dev/virtio/VirtIORng.py.cc -> .os [ SHCXX] RISCV/python/_m5/param_VirtIOConsole.cc -> .os [SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/python/_m5/param_VirtIORng.cc [ SHCXX] RISCV/python/_m5/param_VirtIOBlock.cc -> .os [ SHCXX] RISCV/dev/virtio/VirtIO9P.py.cc -> .os [SO Param] m5.objects.VirtIORng, VirtIORng -> RISCV/params/VirtIORng.hh [ SHCXX] RISCV/python/_m5/param_VirtIORng.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/python/_m5/param_VirtIO9PBase.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/python/_m5/param_VirtIO9PProxy.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> RISCV/params/VirtIO9PBase.hh [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> RISCV/params/VirtIO9PProxy.hh [ SHCXX] RISCV/python/_m5/param_VirtIO9PBase.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/python/_m5/param_VirtIO9PDiod.cc [ SHCXX] RISCV/python/_m5/param_VirtIO9PProxy.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> RISCV/params/VirtIO9PDiod.hh [ SHCXX] RISCV/python/_m5/param_VirtIO9PDiod.cc -> .os [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/python/_m5/param_VirtIO9PSocket.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> RISCV/params/VirtIO9PSocket.hh [ TRACING] -> RISCV/debug/VIO.hh [ SHCXX] src/dev/virtio/base.cc -> RISCV/dev/virtio/base.os [ SHCXX] RISCV/python/_m5/param_VirtIO9PSocket.cc -> .os [ TRACING] -> RISCV/debug/VIOIface.hh [ SHCXX] src/dev/virtio/pci.cc -> RISCV/dev/virtio/pci.os [ TRACING] -> RISCV/debug/VIOConsole.hh [ SHCXX] src/dev/virtio/console.cc -> RISCV/dev/virtio/console.os [ TRACING] -> RISCV/debug/VIOBlock.hh [ SHCXX] src/dev/virtio/block.cc -> RISCV/dev/virtio/block.os [ TRACING] -> RISCV/debug/VIO9P.hh [ TRACING] -> RISCV/debug/VIO9PData.hh [ SHCXX] src/dev/virtio/fs9p.cc -> RISCV/dev/virtio/fs9p.os [ TRACING] -> RISCV/debug/VIORng.hh [ SHCXX] src/dev/virtio/rng.cc -> RISCV/dev/virtio/rng.os [ TRACING] -> RISCV/debug/VIO.cc [ TRACING] -> RISCV/debug/VIORng.cc [ SHCXX] RISCV/debug/VIO.cc -> .os [ SHCXX] RISCV/debug/VIORng.cc -> .os [ TRACING] -> RISCV/debug/VIOIface.cc [ SHCXX] RISCV/debug/VIOIface.cc -> .os [ TRACING] -> RISCV/debug/VIOConsole.cc [ TRACING] -> RISCV/debug/VIOBlock.cc [ SHCXX] RISCV/debug/VIOConsole.cc -> .os [ SHCXX] RISCV/debug/VIOBlock.cc -> .os [ TRACING] -> RISCV/debug/VIO9P.cc [ TRACING] -> RISCV/debug/VIO9PData.cc [ SHCXX] RISCV/debug/VIO9P.cc -> .os [ SHCXX] RISCV/python/m5/defines.py.cc -> .os [ SHCXX] RISCV/debug/VIO9PData.cc -> .os [ SHCXX] RISCV/python/m5/info.py.cc -> .os [ SHCXX] src/base/date.cc -> RISCV/base/date.os [ SHLINK] -> RISCV/libgem5_opt.so scons: done building targets. *** Summary of Warnings *** Warning: Deprecated namespaces are not supported by this compiler. Please make sure to check the mailing list for deprecation announcements. rm -f *.[do] libgem5.so g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder.o sst_responder.cc g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o gem5.o gem5.cc g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst -I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/ -I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext -MMD -MP -c -o sst_responder_subcomponent.o sst_responder_subcomponent.cc In file included from sst_responder.cc:27: sst_responder.hh:50:10: fatal error: sim/sim_object.hh: No such file or directory 50 | #include <sim/sim_object.hh> | ^~~~~~~~~~~~~~~~~~~ compilation terminated. make: *** [<builtin>: sst_responder.o] Error 1 make: *** Waiting for unfinished jobs.... In file included from sst_responder_subcomponent.cc:27: sst_responder_subcomponent.hh:48:10: fatal error: sim/sim_object.hh: No such file or directory 48 | #include <sim/sim_object.hh> | ^~~~~~~~~~~~~~~~~~~ compilation terminated. In file included from gem5.cc:80: gem5.hh:86:10: fatal error: sim/simulate.hh: No such file or directory 86 | #include <sim/simulate.hh> | ^~~~~~~~~~~~~~~~~ compilation terminated. make: *** [<builtin>: sst_responder_subcomponent.o] Error 1 make: *** [<builtin>: gem5.o] Error 1 Build step 'Execute shell' marked build as failure Archiving artifacts

jenkins-no-reply@gem5.org

Fri, Apr 14, 2023 11:34 PM

See https://jenkins.gem5.org/job/nightly/575/display/redirect?page=changes

See <https://jenkins.gem5.org/job/nightly/575/display/redirect?page=changes>