On 8/14/2023 3:47 PM, Khan Shaikhul Hadi wrote: > Instead of directly connecting all level 1 caches ( icache, dcache etc) to CPU and next level bus, I > want to create a controller module that will have all those caches . This controller module will > receive all cpu requests and distribute them to caches. Similarly it will receive all requests to > next level caches and send them to next level cache. The reason I want to do such a thing because, > for my current work, I need to observe requests and responses from caches and modify them based on > some protocol. Initially I thought of modifying the caches all together, but that became more > complicated and I thought if I could connect those caches within a module, that would simplify > things without sacrificing any performance modeling of the caches. Problem is I could not figure out > how to connect the cache simobject cpu and mem side port with the internal port of the controller > module. > > Best > Shaikhul I'd be tempted to make a new subclass of CommMonitor and interpose instances between modules. You could keeps the stats capabilities or not. Regards - EM