Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/66871?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv: Remove Riscv32CPU instance ...................................................................... arch-riscv: Remove Riscv32CPU instance To use riscv 32 bits CPU, we can simply speficy by RiscvXXXCPU parameters like RiscvAtomicSimpleCPU(isa=RiscvISA(riscv_type="RV32"...)) Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66871 Reviewed-by: Jui-min Lee <fcrh@google.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> --- M src/arch/riscv/RiscvCPU.py 1 file changed, 0 insertions(+), 29 deletions(-) Approvals: kokoro: Regressions pass Jui-min Lee: Looks good to me, but someone else must approve Bobby Bruce: Looks good to me, approved; Looks good to me, approved Yu-hsin Wang: Looks good to me, approved diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py index 678c329..1c77045 100644 --- a/src/arch/riscv/RiscvCPU.py +++ b/src/arch/riscv/RiscvCPU.py @@ -23,8 +23,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import functools - from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU @@ -43,13 +41,6 @@ ArchISA = RiscvISA -class Riscv32CPU: - ArchDecoder = RiscvDecoder - ArchMMU = RiscvMMU - ArchInterrupts = RiscvInterrupts - ArchISA = functools.partial(RiscvISA, riscv_type="RV32") - - class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU): mmu = RiscvMMU() @@ -68,23 +59,3 @@ class RiscvMinorCPU(BaseMinorCPU, RiscvCPU): mmu = RiscvMMU() - - -class Riscv32AtomicSimpleCPU(BaseAtomicSimpleCPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32NonCachingSimpleCPU(BaseNonCachingSimpleCPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32TimingSimpleCPU(BaseTimingSimpleCPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32O3CPU(BaseO3CPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32MinorCPU(BaseMinorCPU, Riscv32CPU): - mmu = RiscvMMU() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66871?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5 Gerrit-Change-Number: 66871 Gerrit-PatchSet: 11 Gerrit-Owner: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Gabe Black <gabe.black@gmail.com> Gerrit-Reviewer: Jui-min Lee <fcrh@google.com> Gerrit-Reviewer: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: Yu-hsin Wang <yuhsingw@google.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-CC: Earl Ou <shunhsingou@google.com> Gerrit-CC: Jason Lowe-Power <power.jg@gmail.com>