Hi Shankar,
Thank you for your assistance. Indeed, there are no error messages now.
I'm curious if there would be TLM transaction communication when you connect a TLM memory using this method.
I've managed to get everything running, but there doesn't seem to be any TLM transaction communication happening on my end.
Best Regards,
Zitai
         ----------回复的邮件信息----------
   siva sankar via gem5-users<gem5-users@gem5.org> 在 2023年8月5日 周六 3:09 写道:
Hi Zitai, 
In config_mem() in configs/common/MemConfig.py, commenting out the following worked for me:
if opt_tlm_memory:         system.external_memory = m5.objects.ExternalSlave(             port_type="tlm_slave",             port_data=opt_tlm_memory,             port=system.membus.mem_side_ports,             addr_ranges=system.mem_ranges,         )         #system.workload.addr_check = False --> workload          returnsystem.workload doesn't have the attribute addr_checkThanks, Shankar Gudla 
On Fri, Aug 4, 2023 at 11:45 AM Harshil Patel via gem5-users <gem5-users@gem5.org> wrote:
Hi Zitai,
Here are  some examples of using SystemC with gem5:
https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.pyhttps://github.com/gem5/gem5/tree/develop/util/tlm
However, it should be noted that the integration of SystemC with gem5 is not being actively maintained by the community.
Regards,
Harshil
On Fri, Aug 4, 2023 at 2:31 AM 泰。 via gem5-users <gem5-users@gem5.org> wrote:
Hello All,
I have been searching for a demonstration or example that showcases the integration of Gem5 SE mode with SystemC for the RISC-V architecture.
I am a beginner in Gem5, and I am trying to connect using the following method, but I am facing an 'AttributeError: Class StubWorkload has no parameter addr_check' error. I don't know how to resolve it.
cd util/tlm
../../build/RISCV/gem5.debug ../../configs/example/se.py    
--tlm-memory=transactor                                     
--cpu-type=TimingSimpleCPU                                  
--num-cpu=1                                                 
--mem-type=SimpleMemory                                     
--mem-size=512MB                                            
--mem-channels=1                                            
--cmd=../../tests/test-progs/hello/bin/riscv/linux/hello    
--caches --l2cache
Does the thread below have a final conclusion and examples in the current version of Gem5?
https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64
Best regards,
Zitai
gem5-users mailing list -- gem5-users@gem5.org
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To unsubscribe send an email to gem5-users-leave@gem5.org
--
Thanks and regardsSiva Sankar G
 
                Hi Shankar,
Thank you for your assistance. Indeed, there are no error messages now.
I'm curious if there would be TLM transaction communication when you connect a TLM memory using this method. 
I've managed to get everything running, but there doesn't seem to be any TLM transaction communication happening on my end.
Best Regards,
Zitai
             ----------回复的邮件信息----------
       siva sankar via gem5-users<gem5-users@gem5.org> 在 2023年8月5日 周六 3:09 写道:
Hi Zitai, 
In config_mem() in configs/common/MemConfig.py, commenting out the following worked for me:
  if opt_tlm_memory:         system.external_memory = m5.objects.ExternalSlave(             port_type="tlm_slave",             port_data=opt_tlm_memory,             port=system.membus.mem_side_ports,             addr_ranges=system.mem_ranges,         )         #system.workload.addr_check = False --> workload          returnsystem.workload doesn't have the attribute addr_checkThanks, Shankar Gudla 
On Fri, Aug 4, 2023 at 11:45 AM Harshil Patel via gem5-users <gem5-users@gem5.org> wrote:
Hi Zitai,
Here are  some examples of using SystemC with gem5:
https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.pyhttps://github.com/gem5/gem5/tree/develop/util/tlm
However, it should be noted that the integration of SystemC with gem5 is not being actively maintained by the community.
Regards,
Harshil
On Fri, Aug 4, 2023 at 2:31 AM 泰。 via gem5-users <gem5-users@gem5.org> wrote:
Hello All,
I have been searching for a demonstration or example that showcases the integration of Gem5 SE mode with SystemC for the RISC-V architecture.
I am a beginner in Gem5, and I am trying to connect using the following method, but I am facing an 'AttributeError: Class StubWorkload has no parameter addr_check' error. I don't know how to resolve it.
cd util/tlm
../../build/RISCV/gem5.debug ../../configs/example/se.py    \
--tlm-memory=transactor                                     \
--cpu-type=TimingSimpleCPU                                  \
--num-cpu=1                                                 \
--mem-type=SimpleMemory                                     \
--mem-size=512MB                                            \
--mem-channels=1                                            \
--cmd=../../tests/test-progs/hello/bin/riscv/linux/hello    \
--caches --l2cache
Does the thread below have a final conclusion and examples in the current version of Gem5?
https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64
Best regards,
Zitai
_______________________________________________
 gem5-users mailing list -- gem5-users@gem5.org
 To unsubscribe send an email to gem5-users-leave@gem5.org
 
 _______________________________________________
 gem5-users mailing list -- gem5-users@gem5.org
 To unsubscribe send an email to gem5-users-leave@gem5.org
 
-- 
Thanks and regardsSiva Sankar G