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[S] Change in gem5/gem5[develop]: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

RC
Roger Chang (Gerrit)
Fri, May 12, 2023 12:01 AM

Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70358?usp=email )

Change subject: arch-riscv: Refactor RVC decode flow when funct4==0b1001
and op==C2
......................................................................

arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

the compressed instruction 0x901e (c.add zero, t2) should be decoded as
"c_add zero, t2" not c_ebreak

Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70358
Reviewed-by: Jason Lowe-Power power.jg@gmail.com
Maintainer: Jason Lowe-Power power.jg@gmail.com
Tested-by: kokoro noreply+kokoro@google.com

M src/arch/riscv/isa/decoder.isa
1 file changed, 11 insertions(+), 17 deletions(-)

Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index d89a0c9..f22efb0 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -365,27 +365,21 @@
Rc1 = rvSext(Rc2);
}});
}

  •        0x1: decode RC1 {
    
  •            0x0: SystemOp::c_ebreak({{
    
  •                if (RC2 != 0) {
    
  •                    return std::make_shared<IllegalInstFault>(
    
  •                            "source reg x1", machInst);
    
  •                }
    
  •                return  
    

std::make_shared<BreakpointFault>(xc->pcState());

  •            }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
    
  •            default: decode RC2 {
    
  •                0x0: Jump::c_jalr({{
    
  •                    if (RC1 == 0) {
    
  •                        return std::make_shared<IllegalInstFault>(
    
  •                                "source reg x0", machInst);
    
  •                    }
    
  •        0x1: decode RC2 {
    
  •            0x0: decode RC1 {
    
  •                0x0: SystemOp::c_ebreak({{
    
  •                    return std::make_shared<BreakpointFault>(
    
  •                        xc->pcState());
    
  •                }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
    
  •                default: Jump::c_jalr({{
                        ra = rvSext(NPC);
                        NPC = rvZext(Rc1);
                    }}, IsIndirectControl, IsUncondControl, IsCall);
    
  •                default: CompressedROp::c_add({{
    
  •                    Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
    
  •                }});
                }
    
  •            default: CompressedROp::c_add({{
    
  •                // RC1 == 0 is HINT
    
  •                Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
    
  •            }});
            }
        }
        format CompressedStore {
    

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1
Gerrit-Change-Number: 70358
Gerrit-PatchSet: 7
Gerrit-Owner: Roger Chang rogerycchang@google.com
Gerrit-Reviewer: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Hoa Nguyen hoanguyen@ucdavis.edu
Gerrit-Reviewer: Jason Lowe-Power jason@lowepower.com
Gerrit-Reviewer: Jason Lowe-Power power.jg@gmail.com
Gerrit-Reviewer: Roger Chang rogerycchang@google.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com
Gerrit-CC: Yu-hsin Wang yuhsingw@google.com

Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70358?usp=email ) Change subject: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2 ...................................................................... arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2 the compressed instruction 0x901e (c.add zero, t2) should be decoded as "c_add zero, t2" not c_ebreak Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70358 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/arch/riscv/isa/decoder.isa 1 file changed, 11 insertions(+), 17 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index d89a0c9..f22efb0 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -365,27 +365,21 @@ Rc1 = rvSext(Rc2); }}); } - 0x1: decode RC1 { - 0x0: SystemOp::c_ebreak({{ - if (RC2 != 0) { - return std::make_shared<IllegalInstFault>( - "source reg x1", machInst); - } - return std::make_shared<BreakpointFault>(xc->pcState()); - }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); - default: decode RC2 { - 0x0: Jump::c_jalr({{ - if (RC1 == 0) { - return std::make_shared<IllegalInstFault>( - "source reg x0", machInst); - } + 0x1: decode RC2 { + 0x0: decode RC1 { + 0x0: SystemOp::c_ebreak({{ + return std::make_shared<BreakpointFault>( + xc->pcState()); + }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); + default: Jump::c_jalr({{ ra = rvSext(NPC); NPC = rvZext(Rc1); }}, IsIndirectControl, IsUncondControl, IsCall); - default: CompressedROp::c_add({{ - Rc1_sd = rvSext(Rc1_sd + Rc2_sd); - }}); } + default: CompressedROp::c_add({{ + // RC1 == 0 is HINT + Rc1_sd = rvSext(Rc1_sd + Rc2_sd); + }}); } } format CompressedStore { -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70358?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1 Gerrit-Change-Number: 70358 Gerrit-PatchSet: 7 Gerrit-Owner: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Hoa Nguyen <hoanguyen@ucdavis.edu> Gerrit-Reviewer: Jason Lowe-Power <jason@lowepower.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Roger Chang <rogerycchang@google.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-CC: Yu-hsin Wang <yuhsingw@google.com>