Hi, When I include "clflush" instruction for out-of-order execution simulation in MESITwoLevelCacheHeirarchy, it givis following error: build/X86/mem/ruby/system/RubyPort.cc:433: fatal: Ruby functional read > failed for address 0x1f2b80 Commenting out clflush operations seems to solve the problem. Any idea why it could happen? does CLFLUSH properly implemented in Two Level MESI protocol ? I'm not proficient in gem5 debugging, but what I've observed is that this fatal error is caused by some read request packet, surprisingly not any flush request. Also, If I commented out the fatal error message, system gives warning as follows: build/X86/mem/ruby/system/RubyPort.cc:267: warn: Cache maintenance > operations are not supported in Ruby. and completes execution, no crash or other type of error message. I don't know what "Cache maintenance operations" means here and is it related to the previous error. I'm pretty confused and can't figure out how to approach. Anyone have any suggestions ? I want to understand how clflush operation is simulated in gem5 so that I could modify it for my research needs. I have attached my configuration script and workload C++ file here.

Hi Shaikhul, I think clflush is not supported in Ruby caches at the moment. For reference, here is the original patch that added support for clflush instruction in gem5: arch-x86: Adding clflush, clflushopt, clwb instructions (7401) · Gerrit Code Review (googlesource.com) <https://gem5-review.googlesource.com/c/public/gem5/+/7401> -Ayaz On Fri, Jun 16, 2023 at 2:49 PM Khan Shaikhul Hadi via gem5-users < gem5-users@gem5.org> wrote: > Hi, > When I include "clflush" instruction for out-of-order execution simulation > in MESITwoLevelCacheHeirarchy, it givis following error: > > build/X86/mem/ruby/system/RubyPort.cc:433: fatal: Ruby functional read >> failed for address 0x1f2b80 > > > Commenting out clflush operations seems to solve the problem. Any idea why > it could happen? does CLFLUSH properly implemented in Two Level MESI > protocol ? > > I'm not proficient in gem5 debugging, but what I've observed is that this > fatal error is caused by some read request packet, surprisingly not any > flush request. Also, If I commented out the fatal error message, system > gives warning as follows: > > build/X86/mem/ruby/system/RubyPort.cc:267: warn: Cache maintenance >> operations are not supported in Ruby. > > > and completes execution, no crash or other type of error message. I don't > know what "Cache maintenance operations" means here and is it related to > the previous error. > > I'm pretty confused and can't figure out how to approach. Anyone have any > suggestions ? I want to understand how clflush operation is simulated in > gem5 so that I could modify it for my research needs. I have attached my > configuration script and workload C++ file here. > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-leave@gem5.org >

Hi, Thank you for your response with the patch link. It helped me a lot to understand what's going on and limitations with clflush. Do you have any idea if clflush alternative for arm isa is implemented in gem5 properly or not. I work on persistent memory and for x86 isa, you need clflush and fence ( which also may not be implemented properly). If I move to arm, clflush and fence should be replaced with similar functionality instruction ( I have no idea about arm isa, sorry can't mention explicit instruction. Most likely DC CVAU and memory barrier in arm isa ). Best Shaikhul On Sun, Jun 18, 2023 at 2:55 PM Ayaz Akram <yazakram@ucdavis.edu> wrote: > Hi Shaikhul, > > I think clflush is not supported in Ruby caches at the moment. For > reference, here is the original patch that added support for clflush > instruction in gem5: > > arch-x86: Adding clflush, clflushopt, clwb instructions (7401) · Gerrit > Code Review (googlesource.com) > <https://gem5-review.googlesource.com/c/public/gem5/+/7401> > > -Ayaz > > On Fri, Jun 16, 2023 at 2:49 PM Khan Shaikhul Hadi via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi, >> When I include "clflush" instruction for out-of-order execution >> simulation in MESITwoLevelCacheHeirarchy, it givis following error: >> >> build/X86/mem/ruby/system/RubyPort.cc:433: fatal: Ruby functional read >>> failed for address 0x1f2b80 >> >> >> Commenting out clflush operations seems to solve the problem. Any idea >> why it could happen? does CLFLUSH properly implemented in Two Level MESI >> protocol ? >> >> I'm not proficient in gem5 debugging, but what I've observed is that this >> fatal error is caused by some read request packet, surprisingly not any >> flush request. Also, If I commented out the fatal error message, system >> gives warning as follows: >> >> build/X86/mem/ruby/system/RubyPort.cc:267: warn: Cache maintenance >>> operations are not supported in Ruby. >> >> >> and completes execution, no crash or other type of error message. I don't >> know what "Cache maintenance operations" means here and is it related to >> the previous error. >> >> I'm pretty confused and can't figure out how to approach. Anyone have any >> suggestions ? I want to understand how clflush operation is simulated in >> gem5 so that I could modify it for my research needs. I have attached my >> configuration script and workload C++ file here. >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-leave@gem5.org >> >

On 6/22/2023 8:19 PM, Khan Shaikhul Hadi via gem5-users wrote: > Hi, > Thank you for your response with the patch link. It helped me a lot to understand what's going on > and limitations with clflush. > > Do you have any idea if clflush alternative for arm isa is implemented in gem5 properly or not. I > work on persistent memory and for x86 isa, you need clflush and fence ( which also may not be > implemented properly). If I move to arm, clflush and fence should be replaced with > similar functionality instruction ( I have no idea about arm isa, sorry can't mention explicit > instruction. Most likely DC CVAU and memory barrier in arm isa ). These will boil down to the same micro-ops, just so you know ... EM