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Re: Gem5 SE mode with SystemC for RISC-V

泰。
Tue, Aug 8, 2023 10:30 AM

Hi Harshil,

Thank you for providing the examples.

I tried util/tlm/conf/tlm_slave.py and it works. However, if I directly replace TrafficGen with TimingSimpleCPU, simulation doesn't work. 

Is there a better way to pass transactions to the TLM memory slave when using TimingSimpleCPU as the CPU?Or is this approach feasible?

Regards,
Zitai

         ----------回复的邮件信息----------
   gem5-users@gem5.org<gem5-users@gem5.org&gt;&nbsp;在 2023年8月5日 周六 2:47 写道:

Hi Zitai,

Here are  some examples of using SystemC with gem5:
https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.pyhttps://github.com/gem5/gem5/tree/develop/util/tlm

However, it should be noted that the integration of SystemC with gem5 is not being actively maintained by the community.

Regards,
Harshil

On Fri, Aug 4, 2023 at 2:31 AM 泰。 via gem5-users <gem5-users@gem5.org> wrote:

Hello All,

I have been searching for a demonstration or example that showcases the integration of Gem5 SE mode with SystemC for the RISC-V architecture.

I am a beginner in Gem5, and I am trying to connect using the following method, but I am facing an 'AttributeError: Class StubWorkload has no parameter addr_check' error. I don't know how to resolve it.

cd util/tlm
../../build/RISCV/gem5.debug ../../configs/example/se.py    
--tlm-memory=transactor                                    
--cpu-type=TimingSimpleCPU                                  
--num-cpu=1                                                
--mem-type=SimpleMemory                                    
--mem-size=512MB                                            
--mem-channels=1                                            
--cmd=../../tests/test-progs/hello/bin/riscv/linux/hello    
--caches --l2cache

Does the thread below have a final conclusion and examples in the current version of Gem5?

https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64

Best regards,
Zitai


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Hi&nbsp;Harshil, Thank you for providing the examples. I tried util/tlm/conf/tlm_slave.py and it works. However, if I directly replace TrafficGen with TimingSimpleCPU, simulation doesn't work.&nbsp; Is there a better way to pass transactions to the TLM memory slave when using TimingSimpleCPU as the CPU?Or is this approach feasible? Regards, Zitai ----------回复的邮件信息---------- gem5-users@gem5.org<gem5-users@gem5.org&gt;&nbsp;在 2023年8月5日 周六 2:47 写道: Hi Zitai, Here are&nbsp; some examples of using SystemC with gem5: https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.pyhttps://github.com/gem5/gem5/tree/develop/util/tlm However, it should be noted that the integration of SystemC with gem5 is not being actively maintained by the community. Regards, Harshil On Fri, Aug 4, 2023 at 2:31 AM 泰。 via gem5-users <gem5-users@gem5.org&gt; wrote: Hello All, I have been searching for a demonstration or example that showcases the integration of Gem5 SE mode with SystemC for the RISC-V architecture. I am a beginner in Gem5, and I am trying to connect using the following method, but I am facing an 'AttributeError: Class StubWorkload has no parameter addr_check' error. I don't know how to resolve it. cd util/tlm ../../build/RISCV/gem5.debug ../../configs/example/se.py &nbsp; &nbsp;\ --tlm-memory=transactor &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; \ --cpu-type=TimingSimpleCPU &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;\ --num-cpu=1 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; \ --mem-type=SimpleMemory &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; \ --mem-size=512MB &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;\ --mem-channels=1 &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;\ --cmd=../../tests/test-progs/hello/bin/riscv/linux/hello &nbsp; &nbsp;\ --caches --l2cache Does the thread below have a final conclusion and examples in the current version of Gem5? https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64 Best regards, Zitai _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-leave@gem5.org