Matt Sinclair has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68998?usp=email ) Change subject: mem-ruby: Add RdBypassEvict to stalled GPU L2 requests ...................................................................... mem-ruby: Add RdBypassEvict to stalled GPU L2 requests 66d4a158 added support for AMD's GPU cache modifiers (GLC and SLC). However, it did not consider a corner case with a WB GPU L2 cache where the line is currently in WI and a SLC load arrives at the L2. In this case, we need to stall the load until the write back completes and the line transitions to I. This patch adds that support. Change-Id: I839638c37fdd0f7d25b48a63bca44a3c4d69dbdf --- M src/mem/ruby/protocol/GPU_VIPER-TCC.sm 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm index a595898..8b70431 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm @@ -693,7 +693,7 @@ // Stalling transitions do NOT check the tag array...and if they do, // they can cause a resource stall deadlock! - transition(WI, {RdBlk, WrVicBlk, Atomic, WrVicBlkBack}) { //TagArrayRead} { + transition(WI, {RdBlk, RdBypassEvict, WrVicBlk, Atomic, WrVicBlkBack}) { //TagArrayRead} { // by putting the stalled requests in a buffer, we reduce resource contention // since they won't try again every cycle and will instead only try again once // woken up -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68998?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I839638c37fdd0f7d25b48a63bca44a3c4d69dbdf Gerrit-Change-Number: 68998 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Sinclair <mattdsinclair.wisc@gmail.com> Gerrit-MessageType: newchange