P {margin-top:0;margin-bottom:0;} Regarding the following cache memory latency parameters:

1. Tag latency
2. Data latency
3. Response latency

The default values for "L2 Cache" are 20 cycles per each.

Are those values seem to be practical?

What is the total latency for an access that hits in L2 Cache?

(L1 Miss + L2 Hit)

Should I sum "tag + data + response latency" ?

So 60 cycles only for L2 roundtrip Hit ?

Are the values publicly available for Intel CPUs considers the whole round trip latency?

Which gives 12 cycles only for L2 hit.

ex: https://www.7-cpu.com/cpu/Haswell.html

I found for example the following GEM5 configuration for Intel skylake.

https://github.com/darchr/gem5-skylake-config/blob/master/configuration-details.md

Even that the publicly available hardware latency = 12 cycles for L2 ,

But total round trip = data+ tag + response = 12+12+6=30 cycles.

Thanks.