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   gem5-users@gem5.org<gem5-users@gem5.org&gt;&nbsp;在 2023-07-27 周四 23:08 写道：

Hi Jason: The problem I'm facing is that I replaced it with RiscvTimingSimpleCPU and tried to establish the following connection, but Gem5 threw an error. # Create a system with a Crossbar and a TrafficGenerator as CPU: system =&nbsp;System() system.membus =&nbsp;IOXBar(width=16) system.physmem =&nbsp;( &nbsp; &nbsp; SimpleMemory() ) &nbsp;# This must be instanciated, even if not needed # system.cpu = TrafficGen(config_file="conf/tgen.cfg") system.cpu =&nbsp;RiscvTimingSimpleCPU() system.clk_domain =&nbsp;SrcClockDomain( &nbsp; &nbsp; clock="1.5GHz", voltage_domain=VoltageDomain(voltage="1V") ) # Create a external TLM port: system.tlm =&nbsp;ExternalSlave() system.tlm.addr_ranges =&nbsp;[AddrRange("512MB")] system.tlm.port_type =&nbsp;"tlm_slave" system.tlm.port_data =&nbsp;"transactor" # Route the connections: # system.cpu.port = system.membus.cpu_side_ports system.cpu.icache_port =&nbsp;system.membus.cpu_side_ports system.cpu.dcache_port =&nbsp;system.membus.cpu_side_ports system.cpu.createInterruptController() system.cpu.createThreads() system.system_port =&nbsp;system.membus.cpu_side_ports system.membus.mem_side_ports =&nbsp;system.tlm.port # Start the simulation: root =&nbsp;Root(full_system=False, system=system) root.system.mem_mode =&nbsp;"timing" m5.instantiate() print("Beginning simulation!") exit_event =&nbsp;m5.simulate() &nbsp;# Simulation time specified later on commandline print("Exiting @ tick %i&nbsp;because %s"&nbsp;%&nbsp;(m5.curTick(), exit_event.getCause())) I am unsure about the correct way to establish the connection to the TLM interface. Could you guide me on how to resolve this issue and properly connect the I/D ports of the TimingSimpleCPU to the TLM interface? Thank you very much for your time and attention. Best regards, Zitai ----------回复的邮件信息---------- gem5-users@gem5.org<gem5-users@gem5.org&gt;&nbsp;在 2023-07-27 周四 23:08 写道： Hi Zitai, You should be able to use any CPU model with the TLM interface. You can write your own configuration file / run script that creates a TimingSimpleCPU and connects the I/D ports to the TLM interface.&nbsp; Cheers, Jason On Thu, Jul 27, 2023 at 2:44 AM 泰。 via gem5-users <gem5-users@gem5.org&gt; wrote: Hi： I am a Gem5 user and currently working on system-level modeling and simulation using Gem5. I have encountered an issue and would greatly appreciate your assistance and advice. Currently, I am&nbsp;using tlm_slave.py to connect with TLM memory successfully. However, I noticed that when using tlm_slave.py, it requires pairing with the _TrafficGen CPU which is not a conventional CPU model; instead, it is a special module used for generating memory system stimuli. I would like to use the traditional processor simulator&nbsp;RiscvTimingSimpleCPU instead of the _TrafficGen CPU&nbsp;to conduct more realistic instruction-level simulation. I am not familiar with the method of connecting RiscvTimingSimpleCPU with TLM memory and would like to inquire whether it is possible to achieve this configuration and what specific steps need to be taken. During the configuration process, would I need to modify the interface of RiscvTimingSimpleCPU or perform other customizations? Is the workload significant? Thank you very much for your help and guidance! Best regards, Zitai _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-leave@gem5.org