mem_side_port = RequestPort(
     "This port sends requests and " "receives responses"
)

  panic_on_panic = Param.Bool(

  redistributor = Gicv3CommsTargetSocket("GIC communication target")
  core_reset = IntSinkPin(

          pcstate_decl = (

  opClasses = VectorParam.MinorOpClass(

  opClasses = Param.MinorOpClassSet(
      MinorOpClassSet(),

  cacheStorePorts = Param.Unsigned(

  iewToCommitDelay = Param.Cycles(

  num_cpus = Param.Int("number of cpus / RubyPorts")
  cpuInstDataPort = VectorRequestPort(

  update_limit = Param.Int(

  dump = Param.EtherDump(NULL, "dump object")
  fabric_speed = Param.NetworkBandwidth(

  vrf_gm_bus_latency = Param.Int(

  localMemBarrier = Param.Bool(

  vector_register_file = VectorParam.VectorRegisterFile(

  time_to_wait = Param.Latency("Time before firing the event")
  number_of_fires = Param.Int(

  # one port in each direction
  mem_side_port = RequestPort(

  mem_side_port = RequestPort(

  # one port in each direction
  mem_side_port = RequestPort(

  # histogram of burst length of packets (not using sample period)
  burst_length_bins = Param.Unsigned(

  # enforce a limit on the number of accesses per row
  max_accesses_per_row = Param.Unsigned(

  # A single port for now
  port = ResponsePort(

  addr_ranges = VectorParam.AddrRange(

  # one port in each direction
  mem_side_port = RequestPort(

  # Interface to memory media
  dram = Param.MemInterface(

  # minimum write bursts to schedule before switching back to reads
  min_writes_per_switch = Param.Unsigned(

  mem_side_port = RequestPort(

  req_ports = VectorRequestPort(

  mem_side_port = RequestPort(

  cpu_side_ports = VectorResponsePort(

  vft_assoc = Param.Int(16, "Associativity of the VFT.")

  min_tracked_cache_size = Param.MemorySize(

  system = Param.System(

  version = Param.Int("")
  addr_ranges = VectorParam.AddrRange(

  # The ranges backed by a shadowed ROM
  shadow_rom_ranges = VectorParam.AddrRange(

  for line in simout:
      match = re.match(

Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/66111?usp=email ) Change subject: python: Fix multiline quotes in a single line ...................................................................... python: Fix multiline quotes in a single line An example case, ```python mem_side_port = RequestPort( "This port sends requests and " "receives responses" ) ``` This is the residue of running the python formatter. This is done by finding all tokens matching the regex `"\s"(?![.;"])` and replacing them by empty strings. Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> --- M build_tools/cxx_config_cc.py M build_tools/enum_cc.py M configs/common/Options.py M configs/example/apu_se.py M configs/example/arm/baremetal.py M configs/example/arm/dist_bigLITTLE.py M configs/example/gpufs/amd/AmdGPUOptions.py M configs/example/gpufs/runfs.py M src/arch/arm/ArmFsWorkload.py M src/arch/arm/ArmPMU.py M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py M src/arch/arm/fastmodel/GIC/FastModelGIC.py M src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py M src/arch/isa_parser/isa_parser.py M src/cpu/BaseCPU.py M src/cpu/minor/BaseMinorCPU.py M src/cpu/o3/BaseO3CPU.py M src/cpu/o3/probe/ElasticTrace.py M src/cpu/testers/memtest/MemTest.py M src/cpu/testers/rubytest/RubyTester.py M src/cpu/testers/traffic_gen/BaseTrafficGen.py M src/cpu/testers/traffic_gen/GUPSGen.py M src/cpu/trace/TraceCPU.py M src/dev/amdgpu/AMDGPU.py M src/dev/arm/RealView.py M src/dev/arm/SMMUv3.py M src/dev/net/Ethernet.py M src/dev/pci/PciHost.py M src/dev/serial/Uart.py M src/gpu-compute/GPU.py M src/gpu-compute/LdsState.py M src/learning_gem5/part2/HelloObject.py M src/mem/AddrMapper.py M src/mem/Bridge.py M src/mem/CommMonitor.py M src/mem/DRAMInterface.py M src/mem/DRAMsim3.py M src/mem/ExternalSlave.py M src/mem/MemChecker.py M src/mem/MemCtrl.py M src/mem/MemDelay.py M src/mem/MemInterface.py M src/mem/PortTerminator.py M src/mem/SerialLink.py M src/mem/XBar.py M src/mem/cache/Cache.py M src/mem/cache/compressors/Compressors.py M src/mem/cache/tags/Tags.py M src/mem/probes/StackDistProbe.py M src/mem/ruby/slicc_interface/Controller.py M src/mem/ruby/system/GPUCoalescer.py M src/mem/slicc/symbols/StateMachine.py M src/python/gem5/components/memory/dramsim_3.py M src/python/m5/SimObject.py M src/python/m5/params.py M src/sim/System.py M src/systemc/tests/verify.py M tests/configs/gpu-randomtest-ruby.py M tests/configs/gpu-ruby.py M tests/gem5/fixture.py M util/cpt_upgraders/isa-is-simobject.py M util/gerrit-bot/extract_gitcookies.py M util/maint/list_changes.py M util/maint/show_changes_by_file.py M util/plot_dram/dram_sweep_plot.py 66 files changed, 277 insertions(+), 256 deletions(-) diff --git a/build_tools/cxx_config_cc.py b/build_tools/cxx_config_cc.py index a908aa8..c9ef73e 100644 --- a/build_tools/cxx_config_cc.py +++ b/build_tools/cxx_config_cc.py @@ -256,7 +256,7 @@ code.indent() code("${{param.name}}.clear();") code( - "for (auto i = values.begin(); " "ret && i != values.end(); i ++)" + "for (auto i = values.begin(); ret && i != values.end(); i ++)" ) code("{") code.indent() diff --git a/build_tools/enum_cc.py b/build_tools/enum_cc.py index 476e49d..cd192c5 100644 --- a/build_tools/enum_cc.py +++ b/build_tools/enum_cc.py @@ -87,7 +87,7 @@ ) if enum.wrapper_is_struct: - code("const char *${wrapper_name}::${name}Strings" "[Num_${name}] =") + code("const char *${wrapper_name}::${name}Strings[Num_${name}] =") else: if enum.is_class: code( diff --git a/configs/common/Options.py b/configs/common/Options.py index 81d7791..4ff8115 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -217,7 +217,7 @@ "--maxtime", type=float, default=None, - help="Run to the specified absolute simulated time in " "seconds", + help="Run to the specified absolute simulated time in seconds", ) parser.add_argument( "-P", @@ -691,7 +691,7 @@ "-o", "--options", default="", - help="""The options to pass to the binary, use " " + help="""The options to pass to the binary, use around the entire string""", ) parser.add_argument( diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index 39def02..0b485cf 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -85,7 +85,7 @@ "--cu-per-sqc", type=int, default=4, - help="number of CUs" "sharing an SQC (icache, and thus icache TLB)", + help="number of CUssharing an SQC (icache, and thus icache TLB)", ) parser.add_argument( "--cu-per-scalar-cache", @@ -94,7 +94,7 @@ help="Number of CUs sharing a scalar cache", ) parser.add_argument( - "--simds-per-cu", type=int, default=4, help="SIMD units" "per CU" + "--simds-per-cu", type=int, default=4, help="SIMD unitsper CU" ) parser.add_argument( "--cu-per-sa", @@ -140,13 +140,13 @@ "--glbmem-wr-bus-width", type=int, default=32, - help="VGPR to Coalescer (Global Memory) data bus width " "in bytes", + help="VGPR to Coalescer (Global Memory) data bus width in bytes", ) parser.add_argument( "--glbmem-rd-bus-width", type=int, default=32, - help="Coalescer to VGPR (Global Memory) data bus width in " "bytes", + help="Coalescer to VGPR (Global Memory) data bus width in bytes", ) # Currently we only support 1 local memory pipe parser.add_argument( @@ -166,7 +166,7 @@ "--wfs-per-simd", type=int, default=10, - help="Number of " "WF slots per SIMD", + help="Number of WF slots per SIMD", ) parser.add_argument( @@ -291,12 +291,12 @@ ) parser.add_argument( - "--TLB-prefetch", type=int, help="prefetch depth for" "TLBs" + "--TLB-prefetch", type=int, help="prefetch depth forTLBs" ) parser.add_argument( "--pf-type", type=str, - help="type of prefetch: " "PF_CU, PF_WF, PF_PHASE, PF_STRIDE", + help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE", ) parser.add_argument("--pf-stride", type=int, help="set prefetch stride") parser.add_argument( @@ -369,7 +369,7 @@ type=str, default="gfx801", choices=GfxVersion.vals, - help="Gfx version for gpu" "Note: gfx902 is not fully supported by ROCm", + help="Gfx version for gpuNote: gfx902 is not fully supported by ROCm", ) Ruby.define_options(parser) diff --git a/configs/example/arm/baremetal.py b/configs/example/arm/baremetal.py index 9eeba37..a8db6ba 100644 --- a/configs/example/arm/baremetal.py +++ b/configs/example/arm/baremetal.py @@ -242,25 +242,25 @@ "--semi-stdin", type=str, default="stdin", - help="Standard input for semihosting " "(default: gem5's stdin)", + help="Standard input for semihosting (default: gem5's stdin)", ) parser.add_argument( "--semi-stdout", type=str, default="stdout", - help="Standard output for semihosting " "(default: gem5's stdout)", + help="Standard output for semihosting (default: gem5's stdout)", ) parser.add_argument( "--semi-stderr", type=str, default="stderr", - help="Standard error for semihosting " "(default: gem5's stderr)", + help="Standard error for semihosting (default: gem5's stderr)", ) parser.add_argument( "--semi-path", type=str, default="", - help=("Search path for files to be loaded through " "Arm Semihosting"), + help=("Search path for files to be loaded through Arm Semihosting"), ) parser.add_argument( "args", diff --git a/configs/example/arm/dist_bigLITTLE.py b/configs/example/arm/dist_bigLITTLE.py index a3f3ede..2884a5e 100644 --- a/configs/example/arm/dist_bigLITTLE.py +++ b/configs/example/arm/dist_bigLITTLE.py @@ -51,7 +51,7 @@ def addOptions(parser): # Options for distributed simulation (i.e. dist-gem5) parser.add_argument( - "--dist", action="store_true", help="Distributed gem5" " simulation." + "--dist", action="store_true", help="Distributed gem5 simulation." ) parser.add_argument( "--is-switch", @@ -71,14 +71,14 @@ default=0, action="store", type=int, - help="Number of gem5 processes within the dist gem5" " run.", + help="Number of gem5 processes within the dist gem5 run.", ) parser.add_argument( "--dist-server-name", default="127.0.0.1", action="store", type=str, - help="Name of the message server host\nDEFAULT:" " localhost", + help="Name of the message server host\nDEFAULT: localhost", ) parser.add_argument( "--dist-server-port", diff --git a/configs/example/gpufs/amd/AmdGPUOptions.py b/configs/example/gpufs/amd/AmdGPUOptions.py index 531249e..3d6a8cc 100644 --- a/configs/example/gpufs/amd/AmdGPUOptions.py +++ b/configs/example/gpufs/amd/AmdGPUOptions.py @@ -49,7 +49,7 @@ "--cu-per-sqc", type=int, default=4, - help="number of CUs sharing an SQC" " (icache, and thus icache TLB)", + help="number of CUs sharing an SQC (icache, and thus icache TLB)", ) parser.add_argument( "--cu-per-scalar-cache", @@ -102,19 +102,19 @@ "--issue-period", type=int, default=4, - help="Number of cycles per vector instruction issue" " period", + help="Number of cycles per vector instruction issue period", ) parser.add_argument( "--glbmem-wr-bus-width", type=int, default=32, - help="VGPR to Coalescer (Global Memory) data bus width" " in bytes", + help="VGPR to Coalescer (Global Memory) data bus width in bytes", ) parser.add_argument( "--glbmem-rd-bus-width", type=int, default=32, - help="Coalescer to VGPR (Global Memory) data bus width" " in bytes", + help="Coalescer to VGPR (Global Memory) data bus width in bytes", ) # Currently we only support 1 local memory pipe parser.add_argument( @@ -204,20 +204,20 @@ parser.add_argument( "--LocalMemBarrier", action="store_true", - help="Barrier does not wait for writethroughs to " " complete", + help="Barrier does not wait for writethroughs to complete", ) parser.add_argument( "--countPages", action="store_true", - help="Count Page Accesses and output in " " per-CU output files", + help="Count Page Accesses and output in per-CU output files", ) parser.add_argument( - "--TLB-prefetch", type=int, help="prefetch depth for" "TLBs" + "--TLB-prefetch", type=int, help="prefetch depth for TLBs" ) parser.add_argument( "--pf-type", type=str, - help="type of prefetch: " "PF_CU, PF_WF, PF_PHASE, PF_STRIDE", + help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE", ) parser.add_argument("--pf-stride", type=int, help="set prefetch stride") parser.add_argument( diff --git a/configs/example/gpufs/runfs.py b/configs/example/gpufs/runfs.py index 781ce8e..86b9103 100644 --- a/configs/example/gpufs/runfs.py +++ b/configs/example/gpufs/runfs.py @@ -110,13 +110,13 @@ action="store", type=str, default="16GB", - help="Specify the dGPU physical memory" " size", + help="Specify the dGPU physical memory size", ) parser.add_argument( "--dgpu-num-dirs", type=int, default=1, - help="Set " "the number of dGPU directories (memory controllers", + help="Set the number of dGPU directories (memory controllers", ) parser.add_argument( "--dgpu-mem-type", diff --git a/src/arch/arm/ArmFsWorkload.py b/src/arch/arm/ArmFsWorkload.py index d0dcde7..a9474fe 100644 --- a/src/arch/arm/ArmFsWorkload.py +++ b/src/arch/arm/ArmFsWorkload.py @@ -78,10 +78,10 @@ ) panic_on_panic = Param.Bool( - False, "Trigger a gem5 panic if the " "guest kernel panics" + False, "Trigger a gem5 panic if the guest kernel panics" ) panic_on_oops = Param.Bool( - False, "Trigger a gem5 panic if the " "guest kernel oopses" + False, "Trigger a gem5 panic if the guest kernel oopses" ) diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py index 80288de..f21aaff 100644 --- a/src/arch/arm/ArmPMU.py +++ b/src/arch/arm/ArmPMU.py @@ -88,7 +88,7 @@ or isinstance(newObject, SoftwareIncrement) ): raise TypeError( - "argument must be of ProbeEvent or " "SoftwareIncrement type" + "argument must be of ProbeEvent or SoftwareIncrement type" ) if not self._events: diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py index 577fd53..f690fb5 100644 --- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py +++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py @@ -50,7 +50,7 @@ redistributor = Gicv3CommsTargetSocket("GIC communication target") core_reset = IntSinkPin( - "Raising this signal will put the core into " "reset mode." + "Raising this signal will put the core into reset mode." ) poweron_reset = IntSinkPin( "Power on reset. Initializes all the " diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py index 1e267f0..fe81e72 100644 --- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py +++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py @@ -49,7 +49,7 @@ flash = AmbaInitiatorSocket(64, "Flash") amba = AmbaInitiatorSocket(64, "AMBA initiator socket") core_reset = IntSinkPin( - "Raising this signal will put the core into " "reset mode." + "Raising this signal will put the core into reset mode." ) poweron_reset = IntSinkPin( "Power on reset. Initializes all the " @@ -68,7 +68,7 @@ CFGTE = Param.Bool(False, "Equivalent to CFGTHUMBEXCEPTIONS") RVBARADDR = Param.UInt32(0, "Equivalent to CFGVECTABLE") ase_present = Param.Bool( - True, "Set whether the model has been built " "with NEON support" + True, "Set whether the model has been built with NEON support" ) dcache_size = Param.UInt16(0x8000, "L1 D-Cache size in bytes") flash_enable = Param.Bool(False, "Equivalent to CFGFLASHEN") @@ -88,33 +88,33 @@ "(0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)", ) semihosting_A32_HLT = Param.UInt16( - 0xF000, "A32 HLT number for " "semihosting calls." + 0xF000, "A32 HLT number for semihosting calls." ) semihosting_ARM_SVC = Param.UInt32( - 0x123456, "A32 SVC number for " "semihosting calls." + 0x123456, "A32 SVC number for semihosting calls." ) semihosting_T32_HLT = Param.UInt8( - 60, "T32 HLT number for semihosting " "calls." + 60, "T32 HLT number for semihosting calls." ) semihosting_Thumb_SVC = Param.UInt8( - 171, "T32 SVC number for " "semihosting calls." + 171, "T32 SVC number for semihosting calls." ) semihosting_cmd_line = Param.String( - "", "Command line available to " "semihosting calls." + "", "Command line available to semihosting calls." ) semihosting_cwd = Param.String( - "", "Base directory for semihosting " "file access." + "", "Base directory for semihosting file access." ) semihosting_enable = Param.Bool(True, "Enable semihosting SVC/HLT traps.") semihosting_heap_base = Param.UInt32(0, "Virtual address of heap base.") semihosting_heap_limit = Param.UInt32( - 0xF000000, "Virtual address of " "top of heap." + 0xF000000, "Virtual address of top of heap." ) semihosting_stack_base = Param.UInt32( - 0x10000000, "Virtual address of " "base of descending stack." + 0x10000000, "Virtual address of base of descending stack." ) semihosting_stack_limit = Param.UInt32( - 0xF000000, "Virtual address of " "stack limit." + 0xF000000, "Virtual address of stack limit." ) tcm_a_enable = Param.Bool(False, "Equivalent to CFGTCMBOOT") tcm_a_size = Param.UInt32(0x4000, "Sets the size of the ATCM(in bytes)") @@ -122,7 +122,7 @@ tcm_c_size = Param.UInt32(0x2000, "Sets the size of the CTCM(in bytes)") vfp_dp_present = Param.Bool( True, - "Whether double-precision floating " "point feature is implemented", + "Whether double-precision floating point feature is implemented", ) vfp_enable_at_reset = Param.Bool( False, @@ -171,10 +171,10 @@ PERIPHBASE = Param.UInt32(0x13080000, "Equivalent to CFGPERIPHBASE") cluster_utid = Param.UInt8(0, "Equivalent to CFGCLUSTERUTID") cpi_div = Param.UInt32( - 1, "Divider for calculating CPI " "(Cycles Per Instruction)" + 1, "Divider for calculating CPI (Cycles Per Instruction)" ) cpi_mul = Param.UInt32( - 1, "Multiplier for calculating CPI " "(Cycles Per Instruction)" + 1, "Multiplier for calculating CPI (Cycles Per Instruction)" ) dcache_prefetch_enabled = Param.Bool( False, @@ -194,7 +194,7 @@ "upstream bus, this is only used when dcache-state_modelled=true.", ) dcache_state_modelled = Param.Bool( - False, "Set whether D-cache has " "stateful implementation" + False, "Set whether D-cache has stateful implementation" ) dcache_write_access_latency = Param.UInt64( 0, @@ -206,7 +206,7 @@ "is only used when dcache-state_modelled=true.", ) flash_protection_enable_at_reset = Param.Bool( - False, "Equivalent to " "CFGFLASHPROTEN" + False, "Equivalent to CFGFLASHPROTEN" ) has_flash_protection = Param.Bool(True, "Equivalent to CFGFLASHPROTIMP") icache_prefetch_enabled = Param.Bool( @@ -227,7 +227,7 @@ "upstream bus, this is only used when icache-state_modelled=true.", ) icache_state_modelled = Param.Bool( - False, "Set whether I-cache has " "stateful implementation" + False, "Set whether I-cache has stateful implementation" ) memory_ext_slave_base = Param.UInt32(0, "Equivalent to CFGAXISTCMBASEADDR") memory_flash_base = Param.UInt32(0, "Equivalent to CFGFLASHBASEADDR") @@ -237,16 +237,16 @@ "memory.flash_size = 0 => CFGFLASHIMP = false", ) num_protection_regions_s1 = Param.UInt8( - 16, "Number of v8-R stage1 " "protection regions" + 16, "Number of v8-R stage1 protection regions" ) num_protection_regions_s2 = Param.UInt8( - 16, "Number of v8-R hyp " "protection regions" + 16, "Number of v8-R hyp protection regions" ) num_spi = Param.UInt16( - 960, "Number of interrupts (SPI) into the " "internal GIC controller" + 960, "Number of interrupts (SPI) into the internal GIC controller" ) ram_protection_enable_at_reset = Param.Bool( - False, "Equivalent to " "CFGRAMPROTEN" + False, "Equivalent to CFGRAMPROTEN" ) has_export_m_port = Param.Bool( True, diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py b/src/arch/arm/fastmodel/GIC/FastModelGIC.py index 1ad5a97..ce0a8c5 100644 --- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py +++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py @@ -90,10 +90,10 @@ vPEID_bits = Param.Unsigned(16, "Number of bits of vPEID with GICv4.1.") print_mmap = Param.Bool(False, "Print memory map to stdout") monolithic = Param.Bool( - False, "Indicate that the implementation is not " "distributed" + False, "Indicate that the implementation is not distributed" ) direct_lpi_support = Param.Bool( - False, "Enable support for LPI " "operations through GICR registers" + False, "Enable support for LPI operations through GICR registers" ) cpu_affinities = Param.String( "", @@ -124,42 +124,42 @@ "SPI signalling register aliases(0:Disabled)", ) has_two_security_states = Param.Bool( - True, "If true, has two security " "states" + True, "If true, has two security states" ) DS_fixed_to_zero = Param.Bool( - False, "Enable/disable support of single " "security state" + False, "Enable/disable support of single security state" ) IIDR = Param.UInt32(0x0, "GICD_IIDR and GICR_IIDR value") gicv2_only = Param.Bool( False, - "If true, when using the GICv3 model, " "pretend to be a GICv2 system", + "If true, when using the GICv3 model, pretend to be a GICv2 system", ) STATUSR_implemented = Param.Bool( - True, "Determines whether the " "GICR_STATUSR register is implemented." + True, "Determines whether the GICR_STATUSR register is implemented." ) priority_bits_implemented = Param.Unsigned( - 5, "Number of implemented " "priority bits" + 5, "Number of implemented priority bits" ) itargets_razwi = Param.Bool( - False, "If true, the GICD_ITARGETS registers " "are RAZ/WI" + False, "If true, the GICD_ITARGETS registers are RAZ/WI" ) icfgr_sgi_mask = Param.UInt32( - 0x0, "Mask for writes to ICFGR registers " "that configure SGIs" + 0x0, "Mask for writes to ICFGR registers that configure SGIs" ) icfgr_ppi_mask = Param.UInt32( - 0xAAAAAAAA, "Mask for writes to ICFGR " "registers that configure PPIs" + 0xAAAAAAAA, "Mask for writes to ICFGR registers that configure PPIs" ) icfgr_spi_mask = Param.UInt32( - 0xAAAAAAAA, "Mask for writes to ICFGR " "registers that configure SPIs" + 0xAAAAAAAA, "Mask for writes to ICFGR registers that configure SPIs" ) icfgr_sgi_reset = Param.UInt32( - 0xAAAAAAAA, "Reset value for ICFGR " "registers that configure SGIs" + 0xAAAAAAAA, "Reset value for ICFGR registers that configure SGIs" ) icfgr_ppi_reset = Param.UInt32( - 0x0, "Reset value for ICFGR regesters " "that configure PPIs" + 0x0, "Reset value for ICFGR regesters that configure PPIs" ) icfgr_spi_reset = Param.UInt32( - 0x0, "Reset value for ICFGR regesters " "that configure SPIs" + 0x0, "Reset value for ICFGR regesters that configure SPIs" ) icfgr_ppi_rsvd_bit = Param.Bool( False, @@ -167,16 +167,16 @@ "bits i.e. bit 0,2,4..30 of ICFGRn for n>0", ) igroup_sgi_mask = Param.UInt16( - 0xFFFF, "Mask for writes to SGI bits in " "IGROUP registers" + 0xFFFF, "Mask for writes to SGI bits in IGROUP registers" ) igroup_ppi_mask = Param.UInt16( - 0xFFFF, "Mask for writes to PPI bits in " "IGROUP registers" + 0xFFFF, "Mask for writes to PPI bits in IGROUP registers" ) igroup_sgi_reset = Param.UInt16( - 0x0, "Reset value for SGI bits in IGROUP " "registers" + 0x0, "Reset value for SGI bits in IGROUP registers" ) igroup_ppi_reset = Param.UInt16( - 0x0, "Reset value for SGI bits in IGROUP " "registers" + 0x0, "Reset value for SGI bits in IGROUP registers" ) ppi_implemented_mask = Param.UInt16( 0xFFFF, @@ -220,16 +220,16 @@ "to be instantiated (0=none)", ) its0_base = Param.Addr( - 0, "Register base address for ITS0 " "(automatic if 0)." + 0, "Register base address for ITS0 (automatic if 0)." ) its1_base = Param.Addr( - 0, "Register base address for ITS1 " "(automatic if 0)." + 0, "Register base address for ITS1 (automatic if 0)." ) its2_base = Param.Addr( - 0, "Register base address for ITS2 " "(automatic if 0)." + 0, "Register base address for ITS2 (automatic if 0)." ) its3_base = Param.Addr( - 0, "Register base address for ITS3 " "(automatic if 0)." + 0, "Register base address for ITS3 (automatic if 0)." ) gits_pidr = Param.UInt64( 0x0, @@ -286,52 +286,52 @@ "2 = Virtual Processors; 3 = Physical Processors; 4 = Collections", ) gits_baser0_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER0 register." + 8, "Number of bytes required per entry for GITS_BASER0 register." ) gits_baser1_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER1 register." + 8, "Number of bytes required per entry for GITS_BASER1 register." ) gits_baser2_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER2 register." + 8, "Number of bytes required per entry for GITS_BASER2 register." ) gits_baser3_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER3 register." + 8, "Number of bytes required per entry for GITS_BASER3 register." ) gits_baser4_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER4 register." + 8, "Number of bytes required per entry for GITS_BASER4 register." ) gits_baser5_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER5 register." + 8, "Number of bytes required per entry for GITS_BASER5 register." ) gits_baser6_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER6 register." + 8, "Number of bytes required per entry for GITS_BASER6 register." ) gits_baser7_entry_bytes = Param.Unsigned( - 8, "Number of bytes required per " "entry for GITS_BASER7 register." + 8, "Number of bytes required per entry for GITS_BASER7 register." ) gits_baser0_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER0 register is RAZ/WI." + False, "Indirect field for GITS_BASER0 register is RAZ/WI." ) gits_baser1_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER1 register is RAZ/WI." + False, "Indirect field for GITS_BASER1 register is RAZ/WI." ) gits_baser2_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER2 register is RAZ/WI." + False, "Indirect field for GITS_BASER2 register is RAZ/WI." ) gits_baser3_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER3 register is RAZ/WI." + False, "Indirect field for GITS_BASER3 register is RAZ/WI." ) gits_baser4_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER4 register is RAZ/WI." + False, "Indirect field for GITS_BASER4 register is RAZ/WI." ) gits_baser5_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER5 register is RAZ/WI." + False, "Indirect field for GITS_BASER5 register is RAZ/WI." ) gits_baser6_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER6 register is RAZ/WI." + False, "Indirect field for GITS_BASER6 register is RAZ/WI." ) gits_baser7_indirect_raz = Param.Bool( - False, "Indirect field for " "GITS_BASER7 register is RAZ/WI." + False, "Indirect field for GITS_BASER7 register is RAZ/WI." ) its_baser_force_page_alignement = Param.Bool( True, @@ -352,25 +352,25 @@ "port rather than an AXI4 port).", ) a3_affinity_supported = Param.Bool( - False, "Device supports affinity " "level 3 values that are non-zero." + False, "Device supports affinity level 3 values that are non-zero." ) SGI_RSS_support = Param.Bool( - False, "Device has support for the Range " "Selector feature for SGI" + False, "Device has support for the Range Selector feature for SGI" ) gicr_propbaser_read_only = Param.Bool( - False, "GICR_PROPBASER register is " "read-only." + False, "GICR_PROPBASER register is read-only." ) gicr_propbaser_reset = Param.UInt64( - 0x0, "Value of GICR_PROPBASER on " "reset." + 0x0, "Value of GICR_PROPBASER on reset." ) its_device_bits = Param.Unsigned( - 16, "Number of bits supported for ITS " "device IDs." + 16, "Number of bits supported for ITS device IDs." ) its_entry_size = Param.Unsigned( - 8, "Number of bytes required to store " "each entry in the ITT tables." + 8, "Number of bytes required to store each entry in the ITT tables." ) its_id_bits = Param.Unsigned( - 16, "Number of interrupt bits supported by " "ITS." + 16, "Number of interrupt bits supported by ITS." ) its_collection_id_bits = Param.Unsigned( 0, @@ -386,7 +386,7 @@ "the number supported in memory only. Irrelevant when HCC=0", ) delay_ITS_accesses = Param.Bool( - True, "Delay accesses from the ITS until " "GICR_SYNCR is read." + True, "Delay accesses from the ITS until GICR_SYNCR is read." ) local_SEIs = Param.Bool(False, "Generate SEI to signal internal issues") local_VSEIs = Param.Bool(False, "Generate VSEI to signal internal issues") @@ -397,10 +397,10 @@ "for distributed implementations", ) ITS_hardware_collection_count = Param.Unsigned( - 0, "Number of hardware " "collections held exclusively in the ITS" + 0, "Number of hardware collections held exclusively in the ITS" ) ITS_MOVALL_update_collections = Param.Bool( - False, "Whether MOVALL command " "updates the collection entires" + False, "Whether MOVALL command updates the collection entires" ) ITS_TRANSLATE64R = Param.Bool( False, @@ -409,7 +409,7 @@ "interupt[31:0])", ) enable_protocol_checking = Param.Bool( - False, "Enable/disable protocol " "checking at cpu interface" + False, "Enable/disable protocol checking at cpu interface" ) fixed_routed_spis = Param.String( "", @@ -470,13 +470,13 @@ ) virtual_lpi_support = Param.Bool( False, - "GICv4 Virtual LPIs and Direct " "injection of Virtual LPIs supported", + "GICv4 Virtual LPIs and Direct injection of Virtual LPIs supported", ) virtual_priority_bits = Param.Unsigned( - 5, "Number of implemented virtual " "priority bits" + 5, "Number of implemented virtual priority bits" ) LPI_cache_type = Param.Unsigned( - 1, "Cache type for LPIs, 0:No caching, " "1:Full caching" + 1, "Cache type for LPIs, 0:No caching, 1:Full caching" ) LPI_cache_check_data = Param.Bool( False, @@ -490,7 +490,7 @@ ) DPG_ARE_only = Param.Bool( False, - "Limit application of DPG bits to " "interrupt groups for which ARE=1", + "Limit application of DPG bits to interrupt groups for which ARE=1", ) ARE_fixed_to_one = Param.Bool( False, @@ -498,7 +498,7 @@ "supported and GICD_CTLR.ARE_* is always one", ) legacy_sgi_enable_rao = Param.Bool( - False, "Enables for SGI associated " "with an ARE=0 regime are RAO/WI" + False, "Enables for SGI associated with an ARE=0 regime are RAO/WI" ) pa_size = Param.Unsigned(48, "Number of valid bits in physical address") MSI_IIDR = Param.UInt32(0x0, "Value returned in MSI_IIDR registers.") @@ -763,7 +763,7 @@ "the core fast model.", ) SPI_MBIS = Param.Bool( - True, "Distributor supports meassage based " "signaling of SPI" + True, "Distributor supports meassage based signaling of SPI" ) SPI_unimplemented = Param.String( "", @@ -772,7 +772,7 @@ "'35, 39-42, 73)'", ) irm_razwi = Param.Bool( - False, "GICD_IROUTERn.InterruptRoutingMode is " "RAZ/WI" + False, "GICD_IROUTERn.InterruptRoutingMode is RAZ/WI" ) common_LPI_configuration = Param.Unsigned( 0, @@ -810,7 +810,7 @@ "transient loading state when valid=1", ) allow_LPIEN_clear = Param.Bool( - False, "Allow RW behaviour on " "GICR_CTLR.LPIEN isntead of set once" + False, "Allow RW behaviour on GICR_CTLR.LPIEN isntead of set once" ) GICD_legacy_reg_reserved = Param.Bool( False, diff --git a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py index d6c515c..ad43fed 100644 --- a/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py +++ b/src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py @@ -87,7 +87,7 @@ cache_lines = Param.UInt32(1, "number of cache lines") max_channels = Param.UInt32(8, "virtual channels") controller_nsecure = Param.Bool( - False, "Controller non-secure at reset " "(boot_manager_ns)" + False, "Controller non-secure at reset (boot_manager_ns)" ) irq_nsecure = Param.UInt32(0, "Interrupts non-secure at reset") periph_nsecure = Param.Bool(False, "Peripherals non-secure at reset") diff --git a/src/arch/isa_parser/isa_parser.py b/src/arch/isa_parser/isa_parser.py index 62f3382..aff3c9f 100755 --- a/src/arch/isa_parser/isa_parser.py +++ b/src/arch/isa_parser/isa_parser.py @@ -133,7 +133,7 @@ """ pcstate_decl = ( - f"{self.parser.namespace}::PCState " "__parserAutoPCState;\n" + f"{self.parser.namespace}::PCState __parserAutoPCState;\n" ) myDict["op_decl"] = operands.concatAttrStrings("op_decl") if operands.readPC or operands.setPC: @@ -1098,7 +1098,7 @@ # 'def [signed] bitfield <ID> [<first>:<last>]' # This generates a preprocessor macro in the output file. def p_def_bitfield_0(self, t): - "def_bitfield : DEF opt_signed " "BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI" + "def_bitfield : DEF opt_signed BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI" expr = "bits(machInst, %2d, %2d)" % (t[6], t[8]) if t[2] == "signed": expr = "sext<%d>(%s)" % (t[6] - t[8] + 1, expr) diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 00374d8..438d4f4 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -228,7 +228,7 @@ else: if len(self.isa) != int(self.numThreads): raise RuntimeError( - "Number of ISA instances doesn't " "match thread count" + "Number of ISA instances doesn't match thread count" ) if len(self.decoder) != 0: raise RuntimeError("Decoders should not be set up manually") diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py index 7d15ec4..bcdab1b 100644 --- a/src/cpu/minor/BaseMinorCPU.py +++ b/src/cpu/minor/BaseMinorCPU.py @@ -67,7 +67,7 @@ cxx_class = "gem5::MinorOpClassSet" opClasses = VectorParam.MinorOpClass( - [], "op classes to be matched." " An empty list means any class" + [], "op classes to be matched. An empty list means any class" ) @@ -83,13 +83,13 @@ " (ext_mach_inst & mask) == match", ) suppress = Param.Bool( - False, "if true, this inst. is not executed by" " this FU" + False, "if true, this inst. is not executed by this FU" ) extraCommitLat = Param.Cycles( - 0, "extra cycles to stall commit for" " this inst." + 0, "extra cycles to stall commit for this inst." ) extraCommitLatExpr = Param.TimingExpr( - NULL, "extra cycles as a" " run-time evaluated expression" + NULL, "extra cycles as a run-time evaluated expression" ) extraAssumedLat = Param.Cycles( 0, @@ -109,7 +109,7 @@ " class", ) description = Param.String( - "", "description string of the decoding/inst." " class" + "", "description string of the decoding/inst class" ) @@ -129,11 +129,11 @@ opClasses = Param.MinorOpClassSet( MinorOpClassSet(), - "type of operations" " allowed on this functional unit", + "type of operations allowed on this functional unit", ) opLat = Param.Cycles(1, "latency in cycles") issueLat = Param.Cycles( - 1, "cycles until another instruction can be" " issued" + 1, "cycles until another instruction can be issued" ) timings = VectorParam.MinorFUTiming([], "extra decoding rules") diff --git a/src/cpu/o3/BaseO3CPU.py b/src/cpu/o3/BaseO3CPU.py index 79bd884..b9b0332 100644 --- a/src/cpu/o3/BaseO3CPU.py +++ b/src/cpu/o3/BaseO3CPU.py @@ -79,47 +79,47 @@ activity = Param.Unsigned(0, "Initial count") cacheStorePorts = Param.Unsigned( - 200, "Cache Ports. " "Constrains stores only." + 200, "Cache Ports. Constrains stores only." ) cacheLoadPorts = Param.Unsigned( - 200, "Cache Ports. " "Constrains loads only." + 200, "Cache Ports. Constrains loads only." ) decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") renameToFetchDelay = Param.Cycles(1, "Rename to fetch delay") iewToFetchDelay = Param.Cycles( - 1, "Issue/Execute/Writeback to fetch " "delay" + 1, "Issue/Execute/Writeback to fetch delay" ) commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") fetchWidth = Param.Unsigned(8, "Fetch width") fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") fetchQueueSize = Param.Unsigned( - 32, "Fetch queue size in micro-ops " "per-thread" + 32, "Fetch queue size in micro-ops per-thread" ) renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") iewToDecodeDelay = Param.Cycles( - 1, "Issue/Execute/Writeback to decode " "delay" + 1, "Issue/Execute/Writeback to decode delay" ) commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") decodeWidth = Param.Unsigned(8, "Decode width") iewToRenameDelay = Param.Cycles( - 1, "Issue/Execute/Writeback to rename " "delay" + 1, "Issue/Execute/Writeback to rename delay" ) commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") renameWidth = Param.Unsigned(8, "Rename width") commitToIEWDelay = Param.Cycles( - 1, "Commit to " "Issue/Execute/Writeback delay" + 1, "Commit to Issue/Execute/Writeback delay" ) renameToIEWDelay = Param.Cycles( - 2, "Rename to " "Issue/Execute/Writeback delay" + 2, "Rename to Issue/Execute/Writeback delay" ) issueToExecuteDelay = Param.Cycles( - 1, "Issue to execute delay (internal " "to the IEW stage)" + 1, "Issue to execute delay (internal to the IEW stage)" ) dispatchWidth = Param.Unsigned(8, "Dispatch width") issueWidth = Param.Unsigned(8, "Issue width") @@ -127,7 +127,7 @@ fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") iewToCommitDelay = Param.Cycles( - 1, "Issue/Execute/Writeback to commit " "delay" + 1, "Issue/Execute/Writeback to commit delay" ) renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") commitWidth = Param.Unsigned(8, "Commit width") @@ -166,13 +166,13 @@ 256, "Number of physical integer registers" ) numPhysFloatRegs = Param.Unsigned( - 256, "Number of physical floating point " "registers" + 256, "Number of physical floating point registers" ) numPhysVecRegs = Param.Unsigned( - 256, "Number of physical vector " "registers" + 256, "Number of physical vector registers" ) numPhysVecPredRegs = Param.Unsigned( - 32, "Number of physical predicate " "registers" + 32, "Number of physical predicate registers" ) # most ISAs don't use condition-code regs, so default is 0 numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers") diff --git a/src/cpu/o3/probe/ElasticTrace.py b/src/cpu/o3/probe/ElasticTrace.py index ca4fa4e..73e632f 100644 --- a/src/cpu/o3/probe/ElasticTrace.py +++ b/src/cpu/o3/probe/ElasticTrace.py @@ -44,10 +44,10 @@ # Trace files for the following params are created in the output directory. # User is forced to provide these when an instance of this class is created. instFetchTraceFile = Param.String( - desc="Protobuf trace file name for " "instruction fetch tracing" + desc="Protobuf trace file name for instruction fetch tracing" ) dataDepTraceFile = Param.String( - desc="Protobuf trace file name for " "data dependency tracing" + desc="Protobuf trace file name for data dependency tracing" ) # The dependency window size param must be equal to or greater than the # number of entries in the O3CPU ROB, a typical value is 3 times ROB size @@ -66,5 +66,5 @@ ) # Whether to trace virtual addresses for memory accesses traceVirtAddr = Param.Bool( - False, "Set to true if virtual addresses are " "to be traced." + False, "Set to true if virtual addresses are to be traced." ) diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index e8492b5..24bd974 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -70,7 +70,7 @@ 1000000, "Progress report interval (in accesses)" ) progress_check = Param.Cycles( - 5000000, "Cycles before exiting " "due to lack of progress" + 5000000, "Cycles before exiting due to lack of progress" ) port = RequestPort("Port to the memory system") @@ -79,5 +79,5 @@ # Add the ability to supress error responses on functional # accesses as Ruby needs this suppress_func_errors = Param.Bool( - False, "Suppress panic when " "functional accesses fail." + False, "Suppress panic when functional accesses fail." ) diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index 3fabece..a90cfe1 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -38,7 +38,7 @@ num_cpus = Param.Int("number of cpus / RubyPorts") cpuInstDataPort = VectorRequestPort( - "cpu combo ports to inst & " "data caches" + "cpu combo ports to inst & data caches" ) cpuInstPort = VectorRequestPort("cpu ports to only inst caches") cpuDataPort = VectorRequestPort("cpu ports to only data caches") diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py index b8de198..0d91467 100644 --- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py +++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py @@ -82,7 +82,7 @@ # progress for a long period of time. The default value is # somewhat arbitrary and may well have to be tuned. progress_check = Param.Latency( - "1ms", "Time before exiting " "due to lack of progress" + "1ms", "Time before exiting due to lack of progress" ) # Generator type used for applying Stream and/or Substream IDs to requests diff --git a/src/cpu/testers/traffic_gen/GUPSGen.py b/src/cpu/testers/traffic_gen/GUPSGen.py index 31b5ed3..6b8b3f7 100644 --- a/src/cpu/testers/traffic_gen/GUPSGen.py +++ b/src/cpu/testers/traffic_gen/GUPSGen.py @@ -58,11 +58,11 @@ ) update_limit = Param.Int( - 0, "The number of updates to issue before the" " simulation is over" + 0, "The number of updates to issue before the simulation is over" ) request_queue_size = Param.Int( - 1024, "Maximum number of parallel" " outstanding requests" + 1024, "Maximum number of parallel outstanding requests" ) init_memory = Param.Bool( diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py index e2dc1db..1be1651 100644 --- a/src/cpu/trace/TraceCPU.py +++ b/src/cpu/trace/TraceCPU.py @@ -64,7 +64,7 @@ instTraceFile = Param.String("", "Instruction trace file") dataTraceFile = Param.String("", "Data dependency trace file") sizeStoreBuffer = Param.Unsigned( - 16, "Number of entries in the store " "buffer" + 16, "Number of entries in the store buffer" ) sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer") sizeROB = Param.Unsigned(40, "Number of entries in the re-order buffer") @@ -74,13 +74,13 @@ # changed when frequency is scaled. A default value of 1.0 means the same # frequency as was used for generating the traces. freqMultiplier = Param.Float( - 1.0, "Multiplier scale the Trace CPU " "frequency up or down" + 1.0, "Multiplier scale the Trace CPU frequency up or down" ) # Enable exiting when any one Trace CPU completes execution which is set to # false by default enableEarlyExit = Param.Bool( - False, "Exit when any one Trace CPU " "completes execution" + False, "Exit when any one Trace CPU completes execution" ) # If progress msg interval is set to a non-zero value, it is treated as diff --git a/src/dev/amdgpu/AMDGPU.py b/src/dev/amdgpu/AMDGPU.py index c834d3b..f9d953f 100644 --- a/src/dev/amdgpu/AMDGPU.py +++ b/src/dev/amdgpu/AMDGPU.py @@ -73,7 +73,7 @@ rom_binary = Param.String("ROM binary dumped from hardware") trace_file = Param.String("MMIO trace collected on hardware") checkpoint_before_mmios = Param.Bool( - False, "Take a checkpoint before the" " device begins sending MMIOs" + False, "Take a checkpoint before the device begins sending MMIOs" ) # Specific to Vega10: Vega10 has two SDMA engines these do not have any diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 41e1bcf..0009842 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -117,7 +117,7 @@ pio_addr = Param.Addr("Address for AMBA responder interface") pio_latency = Param.Latency( "10ns", - "Time between action and write/read" "result by AMBA DMA Device", + "Time between action and write/readresult by AMBA DMA Device", ) interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC") amba_id = Param.UInt32("ID of AMBA device for kernel detection") @@ -634,17 +634,17 @@ cxx_header = "dev/arm/hdlcd.hh" cxx_class = "gem5::HDLcd" vnc = Param.VncInput( - Parent.any, "Vnc server for remote frame buffer " "display" + Parent.any, "Vnc server for remote frame buffer display" ) amba_id = 0x00141000 workaround_swap_rb = Param.Bool( - False, "Workaround incorrect color " "selector order in some kernels" + False, "Workaround incorrect color selector order in some kernels" ) workaround_dma_line_count = Param.Bool( - True, "Workaround incorrect " "DMA line count (off by 1)" + True, "Workaround incorrect DMA line count (off by 1)" ) enable_capture = Param.Bool( - True, "capture frame to " "system.framebuffer.{extension}" + True, "capture frame to system.framebuffer.{extension}" ) frame_format = Param.ImageFormat( "Auto", "image format of the captured frame" @@ -655,7 +655,7 @@ pxl_clk = Param.ClockDomain("Pixel clock source") pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") virt_refresh_rate = Param.Frequency( - "20Hz", "Frame refresh rate " "in KVM mode" + "20Hz", "Frame refresh rate in KVM mode" ) _status = "ok" diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py index 415eccd..a1992ec 100644 --- a/src/dev/arm/SMMUv3.py +++ b/src/dev/arm/SMMUv3.py @@ -48,13 +48,13 @@ device_port = ResponsePort("Device port") slave = DeprecatedParam(device_port, "`slave` is now called `device_port`") ats_mem_side_port = RequestPort( - "ATS mem side port," "sends requests and receives responses" + "ATS mem side port,sends requests and receives responses" ) ats_master = DeprecatedParam( ats_mem_side_port, "`ats_master` is now called `ats_mem_side_port`" ) ats_dev_side_port = ResponsePort( - "ATS dev_side_port," "sends responses and receives requests" + "ATS dev_side_port,sends responses and receives requests" ) ats_slave = DeprecatedParam( ats_dev_side_port, "`ats_slave` is now called `ats_dev_side_port`" diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py index 97da54c..608f25b 100644 --- a/src/dev/net/Ethernet.py +++ b/src/dev/net/Ethernet.py @@ -107,7 +107,7 @@ dump = Param.EtherDump(NULL, "dump object") fabric_speed = Param.NetworkBandwidth( - "10Gbps", "switch fabric speed in " "bits per second" + "10Gbps", "switch fabric speed in bits per second" ) interface = VectorEtherInt("Ethernet Interface") output_buffer_size = Param.MemorySize( diff --git a/src/dev/pci/PciHost.py b/src/dev/pci/PciHost.py index ef8a5ab..007b17a 100644 --- a/src/dev/pci/PciHost.py +++ b/src/dev/pci/PciHost.py @@ -57,7 +57,7 @@ conf_base = Param.Addr("Config space base address") conf_size = Param.Addr("Config space base address") conf_device_bits = Param.UInt8( - 8, "Number of bits used to as an " "offset a devices address space" + 8, "Number of bits used to as an offset a devices address space" ) pci_pio_base = Param.Addr(0, "Base address for PCI IO accesses") diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py index f3348d6..2ca68b8 100644 --- a/src/dev/serial/Uart.py +++ b/src/dev/serial/Uart.py @@ -61,7 +61,7 @@ byte_order = Param.ByteOrder("little", "Device byte order") pio_size = Param.Addr(0x4, "Size of address range") end_on_eot = Param.Bool( - False, "End the simulation when a EOT is " "received on the UART" + False, "End the simulation when a EOT is received on the UART" ) diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py index 0fdc0b7..3a87186 100644 --- a/src/gpu-compute/GPU.py +++ b/src/gpu-compute/GPU.py @@ -115,7 +115,7 @@ wf_size = Param.Int(64, "Wavefront size (in work items)") max_ib_size = Param.Int( 13, - "Maximum size (in number of insts) of the " "instruction buffer (IB).", + "Maximum size (in number of insts) of the instruction buffer (IB).", ) @@ -134,32 +134,32 @@ num_SIMDs = Param.Int(4, "number of SIMD units per CU") num_scalar_cores = Param.Int(1, "number of Scalar cores per CU") num_scalar_mem_pipes = Param.Int( - 1, "number of Scalar memory pipelines " "per CU" + 1, "number of Scalar memory pipelines per CU" ) simd_width = Param.Int(16, "width (number of lanes) per SIMD unit") operand_network_length = Param.Int( - 1, "number of pipe stages of operand " "network" + 1, "number of pipe stages of operand network" ) spbypass_pipe_length = Param.Int( - 4, "vector ALU Single Precision bypass " "latency" + 4, "vector ALU Single Precision bypass latency" ) dpbypass_pipe_length = Param.Int( - 4, "vector ALU Double Precision bypass " "latency" + 4, "vector ALU Double Precision bypass latency" ) scalar_pipe_length = Param.Int(1, "number of pipe stages per scalar ALU") issue_period = Param.Int(4, "number of cycles per issue period") vrf_gm_bus_latency = Param.Int( - 1, "number of cycles per use of VRF to " "GM bus" + 1, "number of cycles per use of VRF to GM bus" ) srf_scm_bus_latency = Param.Int( - 1, "number of cycles per use of SRF " "to Scalar Mem bus" + 1, "number of cycles per use of SRF to Scalar Mem bus" ) vrf_lm_bus_latency = Param.Int( - 1, "number of cycles per use of VRF to " "LM bus" + 1, "number of cycles per use of VRF to LM bus" ) num_global_mem_pipes = Param.Int(1, "number of global memory pipes per CU") @@ -194,10 +194,10 @@ system = Param.System(Parent.any, "system object") cu_id = Param.Int("CU id") vrf_to_coalescer_bus_width = Param.Int( - 64, "VRF->Coalescer data bus " "width in bytes" + 64, "VRF->Coalescer data bus width in bytes" ) coalescer_to_vrf_bus_width = Param.Int( - 64, "Coalescer->VRF data bus " "width in bytes" + 64, "Coalescer->VRF data bus width in bytes" ) memory_port = VectorRequestPort("Port to the memory system") @@ -211,7 +211,7 @@ perLaneTLB = Param.Bool(False, "enable per-lane TLB") prefetch_depth = Param.Int( 0, - "Number of prefetches triggered at a time" "(0 turns off prefetching)", + "Number of prefetches triggered at a time(0 turns off prefetching)", ) prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)") prefetch_prev_type = Param.PrefetchType( @@ -225,24 +225,24 @@ functionalTLB = Param.Bool(False, "Assume TLB causes no delay") localMemBarrier = Param.Bool( - False, "Assume Barriers do not wait on " "kernel end" + False, "Assume Barriers do not wait on kernel end" ) countPages = Param.Bool( False, - "Generate per-CU file of all pages " "touched and how many times", + "Generate per-CU file of all pages touched and how many times", ) scalar_mem_queue_size = Param.Int( - 32, "Number of entries in scalar " "memory pipeline's queues" + 32, "Number of entries in scalar memory pipeline's queues" ) global_mem_queue_size = Param.Int( - 256, "Number of entries in the global " "memory pipeline's queues" + 256, "Number of entries in the global memory pipeline's queues" ) local_mem_queue_size = Param.Int( - 256, "Number of entries in the local " "memory pipeline's queues" + 256, "Number of entries in the local memory pipeline's queues" ) max_wave_requests = Param.Int( - 64, "number of pending vector memory " "requests per wavefront" + 64, "number of pending vector memory requests per wavefront" ) max_cu_tokens = Param.Int( 4, @@ -254,18 +254,18 @@ localDataStore = Param.LdsState("the LDS for this CU") vector_register_file = VectorParam.VectorRegisterFile( - "Vector register " "file" + "Vector register file" ) scalar_register_file = VectorParam.ScalarRegisterFile( - "Scalar register " "file" + "Scalar register file" ) out_of_order_data_delivery = Param.Bool( - False, "enable OoO data delivery" " in the GM pipeline" + False, "enable OoO data delivery in the GM pipeline" ) register_manager = Param.RegisterManager("Register Manager") fetch_depth = Param.Int( - 2, "number of i-cache lines that may be " "buffered in the fetch unit." + 2, "number of i-cache lines that may be buffered in the fetch unit." ) diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py index 637cf11..c818593 100644 --- a/src/gpu-compute/LdsState.py +++ b/src/gpu-compute/LdsState.py @@ -41,7 +41,7 @@ size = Param.Int(65536, "the size of the LDS") range = Param.AddrRange("64kB", "address space of the LDS") bankConflictPenalty = Param.Int( - 1, "penalty per LDS bank conflict when " "accessing data" + 1, "penalty per LDS bank conflict when accessing data" ) banks = Param.Int(32, "Number of LDS banks") cuPort = ResponsePort("port that goes to the compute unit") diff --git a/src/learning_gem5/part2/HelloObject.py b/src/learning_gem5/part2/HelloObject.py index 07ffd01..6b9aa8f 100644 --- a/src/learning_gem5/part2/HelloObject.py +++ b/src/learning_gem5/part2/HelloObject.py @@ -36,7 +36,7 @@ time_to_wait = Param.Latency("Time before firing the event") number_of_fires = Param.Int( - 1, "Number of times to fire the event before " "goodbye" + 1, "Number of times to fire the event before goodbye" ) goodbye_object = Param.GoodbyeObject("A goodbye object") @@ -51,5 +51,5 @@ "1kB", "Size of buffer to fill with goodbye" ) write_bandwidth = Param.MemoryBandwidth( - "100MB/s", "Bandwidth to fill " "the buffer" + "100MB/s", "Bandwidth to fill the buffer" ) diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py index 1897236..932fbf1 100644 --- a/src/mem/AddrMapper.py +++ b/src/mem/AddrMapper.py @@ -50,13 +50,13 @@ # one port in each direction mem_side_port = RequestPort( - "This port sends requests and " "receives responses" + "This port sends requests and receives responses" ) master = DeprecatedParam( mem_side_port, "`master` is now called `mem_side_port`" ) cpu_side_port = ResponsePort( - "This port receives requests and " "sends responses" + "This port receives requests and sends responses" ) slave = DeprecatedParam( cpu_side_port, "`slave` is now called `cpu_side_port`" diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index a82f410..8131d62 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -46,13 +46,13 @@ cxx_class = "gem5::Bridge" mem_side_port = RequestPort( - "This port sends requests and " "receives responses" + "This port sends requests and receives responses" ) master = DeprecatedParam( mem_side_port, "`master` is now called `mem_side_port`" ) cpu_side_port = ResponsePort( - "This port receives requests and " "sends responses" + "This port receives requests and sends responses" ) slave = DeprecatedParam( cpu_side_port, "`slave` is now called `cpu_side_port`" diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py index 288aeb5..ab946f1 100644 --- a/src/mem/CommMonitor.py +++ b/src/mem/CommMonitor.py @@ -49,13 +49,13 @@ # one port in each direction mem_side_port = RequestPort( - "This port sends requests and " "receives responses" + "This port sends requests and receives responses" ) master = DeprecatedParam( mem_side_port, "`master` is now called `mem_side_port`" ) cpu_side_port = ResponsePort( - "This port receives requests and " "sends responses" + "This port receives requests and sends responses" ) slave = DeprecatedParam( cpu_side_port, "`slave` is now called `cpu_side_port`" @@ -70,10 +70,10 @@ # histogram of burst length of packets (not using sample period) burst_length_bins = Param.Unsigned( - "20", "# bins in burst length " "histograms" + "20", "# bins in burst length histograms" ) disable_burst_length_hists = Param.Bool( - False, "Disable burst length " "histograms" + False, "Disable burst length histograms" ) # bandwidth per sample period @@ -95,18 +95,18 @@ # outstanding requests (that did not yet get a response) per # sample period outstanding_bins = Param.Unsigned( - "20", "# bins in outstanding " "requests histograms" + "20", "# bins in outstanding requests histograms" ) disable_outstanding_hists = Param.Bool( - False, "Disable outstanding " "requests histograms" + False, "Disable outstanding requests histograms" ) # transactions (requests) observed per sample period transaction_bins = Param.Unsigned( - "20", "# bins in transaction " "count histograms" + "20", "# bins in transaction count histograms" ) disable_transaction_hists = Param.Bool( - False, "Disable transaction count " "histograms" + False, "Disable transaction count histograms" ) # address distributions (heatmaps) with associated address masks diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py index 87bc11b..9c041e5 100644 --- a/src/mem/DRAMInterface.py +++ b/src/mem/DRAMInterface.py @@ -57,7 +57,7 @@ # enforce a limit on the number of accesses per row max_accesses_per_row = Param.Unsigned( - 16, "Max accesses per row before " "closing" + 16, "Max accesses per row before closing" ) # default to 0 bank groups per rank, indicating bank group architecture @@ -139,7 +139,7 @@ # write-to-read, same rank turnaround penalty for same bank group tWTR_L = Param.Latency( Self.tWTR, - "Write to read, same rank switching " "time, same bank group", + "Write to read, same rank switching time, same bank group", ) # minimum precharge to precharge delay time diff --git a/src/mem/DRAMsim3.py b/src/mem/DRAMsim3.py index 0da9c10..40f6160 100644 --- a/src/mem/DRAMsim3.py +++ b/src/mem/DRAMsim3.py @@ -44,11 +44,11 @@ # A single port for now port = ResponsePort( - "port for receiving requests from" "the CPU or other requestor" + "port for receiving requests fromthe CPU or other requestor" ) configFile = Param.String( - "ext/dramsim3/DRAMsim3/configs/" "DDR4_8Gb_x8_2400.ini", + "ext/dramsim3/DRAMsim3/configs/DDR4_8Gb_x8_2400.ini", "The configuration file to use with DRAMSim3", ) filePath = Param.String( diff --git a/src/mem/ExternalSlave.py b/src/mem/ExternalSlave.py index ce2d5b8..b7cd9b2 100644 --- a/src/mem/ExternalSlave.py +++ b/src/mem/ExternalSlave.py @@ -45,7 +45,7 @@ port = SlavePort("Slave port") addr_ranges = VectorParam.AddrRange( - [], "Addresses served by" " this port's external agent" + [], "Addresses served by this port's external agent" ) port_type = Param.String( diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py index 9fc0d7c..fcee653 100644 --- a/src/mem/MemChecker.py +++ b/src/mem/MemChecker.py @@ -51,16 +51,16 @@ # one port in each direction mem_side_port = RequestPort( - "This port sends requests and receives " "responses" + "This port sends requests and receives responses" ) master = DeprecatedParam( - mem_side_port, "`master` is now called " "`mem_side_port`" + mem_side_port, "`master` is now called `mem_side_port`" ) cpu_side_port = ResponsePort( - "This port receives requests and sends " "responses" + "This port receives requests and sends responses" ) slave = DeprecatedParam( - cpu_side_port, "`slave` is now called " "`cpu_side_port`" + cpu_side_port, "`slave` is now called `cpu_side_port`" ) warn_only = Param.Bool(False, "Warn about violations only") memchecker = Param.MemChecker("Instance shared with other monitors") diff --git a/src/mem/MemCtrl.py b/src/mem/MemCtrl.py index c8acd22..549616c 100644 --- a/src/mem/MemCtrl.py +++ b/src/mem/MemCtrl.py @@ -63,7 +63,7 @@ # Interface to memory media dram = Param.MemInterface( - "Memory interface, can be a DRAM" "or an NVM interface " + "Memory interface, can be a DRAMor an NVM interface " ) # read and write buffer depths are set in the interface @@ -79,12 +79,12 @@ # minimum write bursts to schedule before switching back to reads min_writes_per_switch = Param.Unsigned( - 16, "Minimum write bursts before " "switching to reads" + 16, "Minimum write bursts before switching to reads" ) # minimum read bursts to schedule before switching back to writes min_reads_per_switch = Param.Unsigned( - 16, "Minimum read bursts before " "switching to writes" + 16, "Minimum read bursts before switching to writes" ) # scheduler, address map and page policy diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py index 430ffb7..eb4aaa7 100644 --- a/src/mem/MemDelay.py +++ b/src/mem/MemDelay.py @@ -44,13 +44,13 @@ abstract = True mem_side_port = RequestPort( - "This port sends requests and " "receives responses" + "This port sends requests and receives responses" ) master = DeprecatedParam( mem_side_port, "`master` is now called `mem_side_port`" ) cpu_side_port = ResponsePort( - "This port receives requests and " "sends responses" + "This port receives requests and sends responses" ) slave = DeprecatedParam( cpu_side_port, "`slave` is now called `cpu_side_port`" diff --git a/src/mem/MemInterface.py b/src/mem/MemInterface.py index a32a3b5..60bf99b 100644 --- a/src/mem/MemInterface.py +++ b/src/mem/MemInterface.py @@ -73,11 +73,11 @@ device_size = Param.MemorySize("Size of memory device") # the physical organisation of the memory device_bus_width = Param.Unsigned( - "data bus width in bits for each " "memory device/chip" + "data bus width in bits for each memory device/chip" ) burst_length = Param.Unsigned("Burst lenght (BL) in beats") device_rowbuffer_size = Param.MemorySize( - "Page (row buffer) size per " "device/chip" + "Page (row buffer) size per device/chip" ) devices_per_rank = Param.Unsigned("Number of devices/chips per rank") ranks_per_channel = Param.Unsigned("Number of ranks per channel") @@ -96,7 +96,7 @@ # Read/Write requests with data size larger than one full burst are broken # down into multiple requests in the controller tBURST = Param.Latency( - "Burst duration " "(typically burst length / 2 cycles)" + "Burst duration (typically burst length / 2 cycles)" ) # write-to-read, same rank turnaround penalty diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py index 05fdd11..85d0af0 100644 --- a/src/mem/PortTerminator.py +++ b/src/mem/PortTerminator.py @@ -35,8 +35,8 @@ cxx_class = "gem5::PortTerminator" req_ports = VectorRequestPort( - "Vector port for connecting terminating " "response ports." + "Vector port for connecting terminating response ports." ) resp_ports = VectorResponsePort( - "Vector port for terminating " "request ports." + "Vector port for terminating request ports." ) diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py index a40b714..6b76705 100644 --- a/src/mem/SerialLink.py +++ b/src/mem/SerialLink.py @@ -50,13 +50,13 @@ cxx_class = "gem5::SerialLink" mem_side_port = RequestPort( - "This port sends requests and " "receives responses" + "This port sends requests and receives responses" ) master = DeprecatedParam( mem_side_port, "`master` is now called `mem_side_port`" ) cpu_side_port = ResponsePort( - "This port receives requests and " "sends responses" + "This port receives requests and sends responses" ) slave = DeprecatedParam( cpu_side_port, "`slave` is now called `cpu_side_port`" @@ -71,7 +71,7 @@ # link belongs to and the number of lanes: num_lanes = Param.Unsigned( 1, - "Number of parallel lanes inside the serial" "link. (aka. lane width)", + "Number of parallel lanes inside the seriallink. (aka. lane width)", ) link_speed = Param.UInt64( 1, diff --git a/src/mem/XBar.py b/src/mem/XBar.py index dbadccb..d0becc2 100644 --- a/src/mem/XBar.py +++ b/src/mem/XBar.py @@ -51,13 +51,13 @@ cxx_class = "gem5::BaseXBar" cpu_side_ports = VectorResponsePort( - "Vector port for connecting " "mem side ports" + "Vector port for connecting mem side ports" ) slave = DeprecatedParam( cpu_side_ports, "`slave` is now called `cpu_side_ports`" ) mem_side_ports = VectorRequestPort( - "Vector port for connecting " "cpu side ports" + "Vector port for connecting cpu side ports" ) master = DeprecatedParam( mem_side_ports, "`master` is now called `mem_side_ports`" @@ -98,7 +98,7 @@ # a two-level hierarchical lookup. This is useful e.g. for the PCI # xbar configuration. use_default_range = Param.Bool( - False, "Perform address mapping for " "the default port" + False, "Perform address mapping for the default port" ) @@ -130,12 +130,12 @@ # already committed to responding, by establishing if the crossbar # is the point of coherency or not. point_of_coherency = Param.Bool( - False, "Consider this crossbar the " "point of coherency" + False, "Consider this crossbar the point of coherency" ) # Specify whether this crossbar is the point of unification. point_of_unification = Param.Bool( - False, "Consider this crossbar the " "point of unification" + False, "Consider this crossbar the point of unification" ) system = Param.System(Parent.any, "System that the crossbar belongs to.") diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 1dfab19..49665dd 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -61,10 +61,10 @@ # allow whole-line write coalescing, and eventually switches to a # write-no-allocate policy. coalesce_limit = Param.Unsigned( - 2, "Consecutive lines written before " "delaying for coalescing" + 2, "Consecutive lines written before delaying for coalescing" ) no_allocate_limit = Param.Unsigned( - 12, "Consecutive lines written before" " skipping allocation" + 12, "Consecutive lines written before skipping allocation" ) delay_threshold = Param.Unsigned( @@ -129,7 +129,7 @@ # co-allocatable with another existing entry of the same superblock, # so try move the block to co-allocate it move_contractions = Param.Bool( - True, "Try to co-allocate blocks that " "contract" + True, "Try to co-allocate blocks that contract" ) sequential_access = Param.Bool( diff --git a/src/mem/cache/compressors/Compressors.py b/src/mem/cache/compressors/Compressors.py index c8f82c5..eef5f77 100644 --- a/src/mem/cache/compressors/Compressors.py +++ b/src/mem/cache/compressors/Compressors.py @@ -232,7 +232,7 @@ ) check_saturation = Param.Bool( False, - "Whether the counters should be " "manipulated in case of saturation.", + "Whether the counters should be manipulated in case of saturation.", ) vft_assoc = Param.Int(16, "Associativity of the VFT.") diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py index 4e7f632..ade187f 100644 --- a/src/mem/cache/tags/Tags.py +++ b/src/mem/cache/tags/Tags.py @@ -139,7 +139,7 @@ cxx_class = "gem5::FALRU" min_tracked_cache_size = Param.MemorySize( - "128KiB", "Minimum cache size" " for which we track statistics" + "128KiB", "Minimum cache size for which we track statistics" ) # This tag uses its own embedded indexing diff --git a/src/mem/probes/StackDistProbe.py b/src/mem/probes/StackDistProbe.py index 2a9550b..5b44d9d 100644 --- a/src/mem/probes/StackDistProbe.py +++ b/src/mem/probes/StackDistProbe.py @@ -44,7 +44,7 @@ cxx_class = "gem5::StackDistProbe" system = Param.System( - Parent.any, "System to use when determining system cache " "line size" + Parent.any, "System to use when determining system cache line size" ) line_size = Param.Unsigned( diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 185812a..42447f1 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -49,7 +49,7 @@ version = Param.Int("") addr_ranges = VectorParam.AddrRange( - [AllMemory], "Address range this " "controller responds to" + [AllMemory], "Address range this controller responds to" ) cluster_id = Param.UInt32(0, "Id of this controller's cluster") diff --git a/src/mem/ruby/system/GPUCoalescer.py b/src/mem/ruby/system/GPUCoalescer.py index da459de..fcf49e3 100644 --- a/src/mem/ruby/system/GPUCoalescer.py +++ b/src/mem/ruby/system/GPUCoalescer.py @@ -44,7 +44,7 @@ 40 * 64, "max requests (incl. prefetches) outstanding" ) max_coalesces_per_cycle = Param.Int( - 1, "max instructions that can be " "coalesced in a single cycle" + 1, "max instructions that can be coalesced in a single cycle" ) icache = Param.RubyCache("") diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 55ee527..b5af9ca 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -184,7 +184,7 @@ if type_ident == "%s_TBE" % self.ident: if self.TBEType != None: self.error( - "Multiple Transaction Buffer types in a " "single machine." + "Multiple Transaction Buffer types in a single machine." ) self.TBEType = type diff --git a/src/python/gem5/components/memory/dramsim_3.py b/src/python/gem5/components/memory/dramsim_3.py index b7eba91..e5c1877 100644 --- a/src/python/gem5/components/memory/dramsim_3.py +++ b/src/python/gem5/components/memory/dramsim_3.py @@ -53,7 +53,7 @@ ) elif os.path.isfile(input_file): raise Exception( - "The configuration file '" + input_file + "' cannot " " be found." + "The configuration file '" + input_file + "' cannot be found." ) output_file = "/tmp/" + mem_type + "_chnls" + str(num_chnls) + ".ini" diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 91cbbc5..b5dfca9 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -478,7 +478,7 @@ args, varargs, keywords, defaults = inspect.getargspec(func) if varargs or keywords: raise ValueError( - "Wrapped methods must not contain variable " "arguments" + "Wrapped methods must not contain variable arguments" ) # Create tuples of (argument, default) @@ -571,7 +571,7 @@ setattr(sim_object, key, val) else: raise SimObjectCliWrapperException( - "tried to set or unsettable" "object parameter: " + key + "tried to set or unsettableobject parameter: " + key ) else: raise SimObjectCliWrapperException( diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 8e96f46..e76380b 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -1457,7 +1457,7 @@ cls.map[val] = idx else: raise TypeError( - "Enum-derived class must define " "attribute 'map' or 'vals'" + "Enum-derived class must define attribute 'map' or 'vals'" ) if cls.is_class: diff --git a/src/sim/System.py b/src/sim/System.py index a5722e8..eb1280f 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -77,7 +77,7 @@ # mmap). By enabling this flag, we accommodate cases where a large # (but sparse) memory is simulated. mmap_using_noreserve = Param.Bool( - False, "mmap the backing store " "without reserving swap" + False, "mmap the backing store without reserving swap" ) # The memory ranges are to be populated when creating the system @@ -89,7 +89,7 @@ # The ranges backed by a shadowed ROM shadow_rom_ranges = VectorParam.AddrRange( - [], "Ranges backed by a " "shadowed ROM" + [], "Ranges backed by a shadowed ROM" ) shared_backstore = Param.String( diff --git a/src/systemc/tests/verify.py b/src/systemc/tests/verify.py index 5191062..0d8ce3c 100755 --- a/src/systemc/tests/verify.py +++ b/src/systemc/tests/verify.py @@ -148,7 +148,7 @@ "--timeout", type=int, metavar="SECONDS", - help="Time limit for each run in seconds, " "0 to disable.", + help="Time limit for each run in seconds, 0 to disable.", default=60, ) parser.add_argument( @@ -604,7 +604,7 @@ filter_opts.add_argument( "--filter", default="True", - help="Python expression which filters tests based " "on their properties", + help="Python expression which filters tests based on their properties", ) filter_opts.add_argument( "--filter-file", diff --git a/tests/configs/gpu-randomtest-ruby.py b/tests/configs/gpu-randomtest-ruby.py index ceede7f..cfc6552 100644 --- a/tests/configs/gpu-randomtest-ruby.py +++ b/tests/configs/gpu-randomtest-ruby.py @@ -57,7 +57,7 @@ help="Number of GPU Command Processors (CP)", ) parser.add_argument( - "--simds-per-cu", type=int, default=4, help="SIMD units" "per CU" + "--simds-per-cu", type=int, default=4, help="SIMD unitsper CU" ) parser.add_argument( "--wf-size", type=int, default=64, help="Wavefront size(in workitems)" @@ -66,7 +66,7 @@ "--wfs-per-simd", type=int, default=10, - help="Number of " "WF slots per SIMD", + help="Number of WF slots per SIMD", ) # Add the ruby specific and protocol specific options diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py index e45c446..cd330ea 100644 --- a/tests/configs/gpu-ruby.py +++ b/tests/configs/gpu-ruby.py @@ -79,13 +79,13 @@ help="Number of GPU Command Processors (CP)", ) parser.add_argument( - "--simds-per-cu", type=int, default=4, help="SIMD units" "per CU" + "--simds-per-cu", type=int, default=4, help="SIMD unitsper CU" ) parser.add_argument( "--cu-per-sqc", type=int, default=4, - help="number of CUs" "sharing an SQC (icache, and thus icache TLB)", + help="number of CUssharing an SQC (icache, and thus icache TLB)", ) parser.add_argument( "--wf-size", type=int, default=64, help="Wavefront size(in workitems)" @@ -94,7 +94,7 @@ "--wfs-per-simd", type=int, default=8, - help="Number of " "WF slots per SIMD", + help="Number of WF slots per SIMD", ) parser.add_argument( "--sp-bypass-path-length", @@ -195,12 +195,12 @@ help="Count Page Accesses and output in per-CU output files", ) parser.add_argument( - "--TLB-prefetch", type=int, help="prefetch depth for" "TLBs" + "--TLB-prefetch", type=int, help="prefetch depth forTLBs" ) parser.add_argument( "--pf-type", type=str, - help="type of prefetch: " "PF_CU, PF_WF, PF_PHASE, PF_STRIDE", + help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE", ) parser.add_argument("--pf-stride", type=int, help="set prefetch stride") parser.add_argument( diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py index 65b5454..c8bc79f 100644 --- a/tests/gem5/fixture.py +++ b/tests/gem5/fixture.py @@ -170,7 +170,7 @@ ) else: log.test_log.message( - "Building the following targets." " This may take a while." + "Building the following targets. This may take a while." ) log.test_log.message("%s" % (", ".join(self.targets))) log.test_log.message( @@ -391,7 +391,7 @@ except (urllib.error.URLError, socket.timeout): # Problem checking the server, use the old files. log.test_log.debug( - "Could not contact server. " "Binaries may be old." + "Could not contact server. Binaries may be old." ) return # If the server version is more recent, download it diff --git a/util/cpt_upgraders/isa-is-simobject.py b/util/cpt_upgraders/isa-is-simobject.py index 3f0132c..077d4d9 100644 --- a/util/cpt_upgraders/isa-is-simobject.py +++ b/util/cpt_upgraders/isa-is-simobject.py @@ -94,7 +94,7 @@ else: if cpt.items(sec): raise ValueError( - "Unexpected populated ISA section in old " "checkpoint" + "Unexpected populated ISA section in old checkpoint" ) for (key, value) in options: diff --git a/util/gerrit-bot/extract_gitcookies.py b/util/gerrit-bot/extract_gitcookies.py index 24f2ca0..ef17be1 100755 --- a/util/gerrit-bot/extract_gitcookies.py +++ b/util/gerrit-bot/extract_gitcookies.py @@ -62,7 +62,7 @@ ) parser.add_argument( "input", - help=("Path to a .gitcookies file or a file with " "a similar format"), + help=("Path to a .gitcookies file or a file with a similar format"), ) parser.add_argument("output", help="Path to the output file") args = parser.parse_args() diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py index 9ada2b5..465ae1abb 100755 --- a/util/maint/list_changes.py +++ b/util/maint/list_changes.py @@ -179,14 +179,14 @@ "-u", type=str, default="origin/master", - help="Upstream branch for comparison. " "Default: %(default)s", + help="Upstream branch for comparison. Default: %(default)s", ) parser.add_argument( "--feature", "-f", type=str, default="HEAD", - help="Feature branch for comparison. " "Default: %(default)s", + help="Feature branch for comparison. Default: %(default)s", ) parser.add_argument( "--show-unknown", @@ -199,7 +199,7 @@ parser.add_argument( "--deep-search", action="store_true", - help="Use a deep search to find incorrectly " "rebased changes", + help="Use a deep search to find incorrectly rebased changes", ) parser.add_argument( "paths", diff --git a/util/maint/show_changes_by_file.py b/util/maint/show_changes_by_file.py index be22262..ea739f7 100755 --- a/util/maint/show_changes_by_file.py +++ b/util/maint/show_changes_by_file.py @@ -95,14 +95,14 @@ "-u", type=str, default="origin/master", - help="Upstream branch for comparison. " "Default: %(default)s", + help="Upstream branch for comparison. Default: %(default)s", ) parser.add_argument( "--feature", "-f", type=str, default="HEAD", - help="Feature branch for comparison. " "Default: %(default)s", + help="Feature branch for comparison. Default: %(default)s", ) parser.add_argument( "paths", diff --git a/util/plot_dram/dram_sweep_plot.py b/util/plot_dram/dram_sweep_plot.py index 8acb6ab..ad7bc5e 100755 --- a/util/plot_dram/dram_sweep_plot.py +++ b/util/plot_dram/dram_sweep_plot.py @@ -90,7 +90,7 @@ for line in simout: match = re.match( - "DRAM sweep with " "burst: (\d+), banks: (\d+), max stride: (\d+)", + "DRAM sweep with burst: (\d+), banks: (\d+), max stride: (\d+)", line, ) if match: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/66111?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icf223bbe889e5fa5749a81ef77aa6e721f38b549 Gerrit-Change-Number: 66111 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen <hoanguyen@ucdavis.edu> Gerrit-MessageType: newchange