Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68797?usp=email ) Change subject: stdlib: remove useless cache init function ...................................................................... stdlib: remove useless cache init function Removing the __init__ function allows to modify the cache members without having to add a new parameter in the __init__ function. Also add default size to caches as passing the size of the caches will become optional. Change-Id: If7c1f03763eee88994bfcf11745b79fcce38191f --- M src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py M src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py M src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py 3 files changed, 31 insertions(+), 83 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py index da4a4ea..12cd5b9 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py @@ -26,38 +26,20 @@ from .....utils.override import * -from m5.objects import Cache, BasePrefetcher, StridePrefetcher - -from typing import Type +from m5.objects import Cache, StridePrefetcher class L1DCache(Cache): """ A simple L1 data cache with default values. - - If the cache has a mostly exclusive downstream cache, writeback_clean - should be set to True. """ - def __init__( - self, - size: str, - assoc: int = 8, - tag_latency: int = 1, - data_latency: int = 1, - response_latency: int = 1, - mshrs: int = 16, - tgts_per_mshr: int = 20, - writeback_clean: bool = False, - PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, - ): - super().__init__() - self.size = size - self.assoc = assoc - self.tag_latency = tag_latency - self.data_latency = data_latency - self.response_latency = response_latency - self.mshrs = mshrs - self.tgts_per_mshr = tgts_per_mshr - self.writeback_clean = writeback_clean - self.prefetcher = PrefetcherCls() + size = "32kB" + assoc = 8 + tag_latency = 1 + data_latency = 1 + response_latency = 1 + mshrs = 16 + tgts_per_mshr = 20 + writeback_clean = False + prefetcher = StridePrefetcher() diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py index f1ac89c..fa33a02 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py @@ -24,9 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Type - -from m5.objects import Cache, BasePrefetcher, StridePrefetcher +from m5.objects import Cache, StridePrefetcher from .....utils.override import * @@ -34,30 +32,14 @@ class L1ICache(Cache): """ A simple L1 instruction cache with default values. - - If the cache does not have a downstream cache or the downstream cache - is mostly inclusive as usual, writeback_clean should be set to False. """ - def __init__( - self, - size: str, - assoc: int = 8, - tag_latency: int = 1, - data_latency: int = 1, - response_latency: int = 1, - mshrs: int = 16, - tgts_per_mshr: int = 20, - writeback_clean: bool = True, - PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, - ): - super().__init__() - self.size = size - self.assoc = assoc - self.tag_latency = tag_latency - self.data_latency = data_latency - self.response_latency = response_latency - self.mshrs = mshrs - self.tgts_per_mshr = tgts_per_mshr - self.writeback_clean = writeback_clean - self.prefetcher = PrefetcherCls() + size = "32kB" + assoc = 8 + tag_latency = 1 + data_latency = 1 + response_latency = 1 + mshrs = 16 + tgts_per_mshr = 20 + writeback_clean = True + prefetcher = StridePrefetcher() diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py index 86b6985..6329b56 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py @@ -26,9 +26,7 @@ from .....utils.override import * -from m5.objects import Cache, Clusivity, BasePrefetcher, StridePrefetcher - -from typing import Type +from m5.objects import Cache, StridePrefetcher class L2Cache(Cache): @@ -36,27 +34,13 @@ A simple L2 Cache with default values. """ - def __init__( - self, - size: str, - assoc: int = 16, - tag_latency: int = 10, - data_latency: int = 10, - response_latency: int = 1, - mshrs: int = 20, - tgts_per_mshr: int = 12, - writeback_clean: bool = False, - clusivity: Clusivity = "mostly_incl", - PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, - ): - super().__init__() - self.size = size - self.assoc = assoc - self.tag_latency = tag_latency - self.data_latency = data_latency - self.response_latency = response_latency - self.mshrs = mshrs - self.tgts_per_mshr = tgts_per_mshr - self.writeback_clean = writeback_clean - self.clusivity = clusivity - self.prefetcher = PrefetcherCls() + size = "512kB" + assoc = 16 + tag_latency = 10 + data_latency = 10 + response_latency = 1 + mshrs = 20 + tgts_per_mshr = 12 + writeback_clean = False + clusivity = "mostly_incl" + prefetcher = StridePrefetcher() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68797?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If7c1f03763eee88994bfcf11745b79fcce38191f Gerrit-Change-Number: 68797 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Rollet <tom.rollet@huawei.com> Gerrit-MessageType: newchange