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[S] Change in gem5/gem5[develop]: arch-riscv: Implemented zicbom/zicboz extensions for RISC V

ZM
Zack McKevitt (Gerrit)
Thu, Jun 29, 2023 11:23 PM

Zack McKevitt has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71958?usp=email )

Change subject: arch-riscv: Implemented zicbom/zicboz extensions for RISC V
......................................................................

arch-riscv: Implemented zicbom/zicboz extensions for RISC V

Change-Id: I79d0e6059a2dbb5a0057c4f7489b999f9e803684

M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/mem.isa
2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index a339c11..cf55a4a 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -509,6 +509,23 @@
0x1: fence_i({{
}}, uint64_t, IsNonSpeculative, IsSerializeAfter,
No_OpClass);
}
+

  •        0x2: decode FUNCT12 {
    
  •            format CBMOp {
    
  •                0x0: cbo_inval({{
    
  •                    Mem = 0;
    
  •                }}, mem_flags=[INVALIDATE, DST_POC]);
    
  •                0x1: cbo_clean({{
    
  •                    Mem = 0;
    
  •                }}, mem_flags=[CLEAN, DST_POC]);
    
  •                0x2: cbo_flush({{
    
  •                    Mem = 0;
    
  •                }}, mem_flags=[CLEAN, INVALIDATE, DST_POC]);
    
  •                0x4: cbo_zero({{
    
  •                    Mem = 0;
    
  •                }}, mem_flags=[CACHE_BLOCK_ZERO]);
    
  •            }
    
  •        }
        }
    
        0x04: decode FUNCT3 {
    

diff --git a/src/arch/riscv/isa/formats/mem.isa
b/src/arch/riscv/isa/formats/mem.isa
index 0d80260..7cec113 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -243,3 +243,10 @@
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code,
mem_flags,
inst_flags, 'Store', exec_template_base='Store')
}};
+
+def format CBMOp(memacc_code, ea_code={{EA = rvZext(Rs1 + offset);}},

  •    offset_code={{offset = 0;}}, mem_flags=[], inst_flags=[]) {{
    
  • (header_output, decoder_output, decode_block, exec_output) = \
  •    LoadStoreBase(name, Name, offset_code, ea_code, memacc_code,  
    

mem_flags,

  •    inst_flags, 'Store', exec_template_base='Store')
    

+}};

--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79d0e6059a2dbb5a0057c4f7489b999f9e803684
Gerrit-Change-Number: 71958
Gerrit-PatchSet: 1
Gerrit-Owner: Zack McKevitt zack.mckevitt@gmail.com

Zack McKevitt has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71958?usp=email ) Change subject: arch-riscv: Implemented zicbom/zicboz extensions for RISC V ...................................................................... arch-riscv: Implemented zicbom/zicboz extensions for RISC V Change-Id: I79d0e6059a2dbb5a0057c4f7489b999f9e803684 --- M src/arch/riscv/isa/decoder.isa M src/arch/riscv/isa/formats/mem.isa 2 files changed, 24 insertions(+), 0 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index a339c11..cf55a4a 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -509,6 +509,23 @@ 0x1: fence_i({{ }}, uint64_t, IsNonSpeculative, IsSerializeAfter, No_OpClass); } + + 0x2: decode FUNCT12 { + format CBMOp { + 0x0: cbo_inval({{ + Mem = 0; + }}, mem_flags=[INVALIDATE, DST_POC]); + 0x1: cbo_clean({{ + Mem = 0; + }}, mem_flags=[CLEAN, DST_POC]); + 0x2: cbo_flush({{ + Mem = 0; + }}, mem_flags=[CLEAN, INVALIDATE, DST_POC]); + 0x4: cbo_zero({{ + Mem = 0; + }}, mem_flags=[CACHE_BLOCK_ZERO]); + } + } } 0x04: decode FUNCT3 { diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index 0d80260..7cec113 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -243,3 +243,10 @@ LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, inst_flags, 'Store', exec_template_base='Store') }}; + +def format CBMOp(memacc_code, ea_code={{EA = rvZext(Rs1 + offset);}}, + offset_code={{offset = 0;}}, mem_flags=[], inst_flags=[]) {{ + (header_output, decoder_output, decode_block, exec_output) = \ + LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, + inst_flags, 'Store', exec_template_base='Store') +}}; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71958?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I79d0e6059a2dbb5a0057c4f7489b999f9e803684 Gerrit-Change-Number: 71958 Gerrit-PatchSet: 1 Gerrit-Owner: Zack McKevitt <zack.mckevitt@gmail.com>