// AArch32 CP15 registers
  InitReg(MISCREG_MIDR)

Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email ) Change subject: arch-arm: Remove ISA::initID32 ...................................................................... arch-arm: Remove ISA::initID32 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6 Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70467 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> --- M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/regs/misc.cc 3 files changed, 46 insertions(+), 54 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Richard Cooper: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 4033d0f..8424db5 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -142,8 +142,6 @@ miscRegs[idx] = lookUpMiscReg[idx].reset(); } - initID32(p); - // We always initialize AArch64 ID registers even // if we are in AArch32. This is done since if we // are in SE mode we don't know if our ArmProcess is @@ -258,57 +256,6 @@ } void -ISA::initID32(const ArmISAParams &p) -{ - // Initialize configurable default values - - uint32_t midr; - if (p.midr != 0x0) - midr = p.midr; - else if (highestELIs64) - // Cortex-A57 TRM r0p0 MIDR - midr = 0x410fd070; - else - // Cortex-A15 TRM r0p0 MIDR - midr = 0x410fc0f0; - - miscRegs[MISCREG_MIDR] = midr; - miscRegs[MISCREG_VPIDR] = midr; - - miscRegs[MISCREG_ID_ISAR0] = p.id_isar0; - miscRegs[MISCREG_ID_ISAR1] = p.id_isar1; - miscRegs[MISCREG_ID_ISAR2] = p.id_isar2; - miscRegs[MISCREG_ID_ISAR3] = p.id_isar3; - miscRegs[MISCREG_ID_ISAR4] = p.id_isar4; - - miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0; - miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1; - miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2; - miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3; - miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4; - - ISAR5 isar5 = p.id_isar5; - if (release->has(ArmExtension::CRYPTO)) { - isar5.crc32 = 1; - isar5.sha2 = 1; - isar5.sha1 = 1; - isar5.aes = 2; - } else { - isar5.crc32 = 0; - isar5.sha2 = 0; - isar5.sha1 = 0; - isar5.aes = 0; - } - isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; - isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0; - miscRegs[MISCREG_ID_ISAR5] = isar5; - - ISAR6 isar6 = p.id_isar6; - isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0; - miscRegs[MISCREG_ID_ISAR6] = isar6; -} - -void ISA::initID64(const ArmISAParams &p) { // Initialize configurable id registers diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 5dd1b38..8419641 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -172,7 +172,6 @@ protected: void clear32(const ArmISAParams &p); void clear64(const ArmISAParams &p); - void initID32(const ArmISAParams &p); void initID64(const ArmISAParams &p); void addressTranslation(MMU::ArmTranslationType tran_type, diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 3b23a20..f5e2502 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -45,6 +45,7 @@ #include "cpu/thread_context.hh" #include "dev/arm/gic_v3_cpu_interface.hh" #include "sim/full_system.hh" +#include "params/ArmISA.hh" namespace gem5 { @@ -2116,6 +2117,17 @@ const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE); const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2); + const Params &p(params()); + + uint32_t midr; + if (p.midr != 0x0) + midr = p.midr; + else if (highestELIs64) + // Cortex-A57 TRM r0p0 MIDR + midr = 0x410fd070; + else + // Cortex-A15 TRM r0p0 MIDR + midr = 0x410fc0f0; /** * Some registers alias with others, and therefore need to be translated. @@ -2465,6 +2477,7 @@ // AArch32 CP15 registers InitReg(MISCREG_MIDR) + .reset(midr) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CTR) .allPrivileges().exceptUserMode().writes(0); @@ -2488,28 +2501,60 @@ InitReg(MISCREG_ID_AFR0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR0) + .reset(p.id_mmfr0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR1) + .reset(p.id_mmfr1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR2) + .reset(p.id_mmfr2) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR3) + .reset(p.id_mmfr3) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR4) + .reset(p.id_mmfr4) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR0) + .reset(p.id_isar0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR1) + .reset(p.id_isar1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR2) + .reset(p.id_isar2) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR3) + .reset(p.id_isar3) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR4) + .reset(p.id_isar4) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR5) + .reset([p,release=release] () { + ISAR5 isar5 = p.id_isar5; + if (release->has(ArmExtension::CRYPTO)) { + isar5.crc32 = 1; + isar5.sha2 = 1; + isar5.sha1 = 1; + isar5.aes = 2; + } else { + isar5.crc32 = 0; + isar5.sha2 = 0; + isar5.sha1 = 0; + isar5.aes = 0; + } + isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; + isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0; + return isar5; + }()) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR6) + .reset([p,release=release] () { + ISAR6 isar6 = p.id_isar6; + isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0; + return isar6; + }()) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CCSIDR) .allPrivileges().exceptUserMode().writes(0); @@ -2527,6 +2572,7 @@ .bankedChild() .secure().exceptUserMode(); InitReg(MISCREG_VPIDR) + .reset(midr) .hyp().monNonSecure(); InitReg(MISCREG_VMPIDR) .hyp().monNonSecure(); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6 Gerrit-Change-Number: 70467 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Andreas Sandberg <andreas.sandberg@arm.com> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>