Dear gem5-ers -- I am thinking of trying to put together something that roughly models ARM's R82, which is an 8-stage, width 3, in order cpu. (It's also not a single thing, but has numerous options you choose, and then set up RTL and can have your design manufactured.) I see that there are three non-SMT and one SMT in order pipeline models, but I'm not clear how I would use them -- swap them in for the one that does not have 5, 9, or smt in its name? Or what? I do know that I'll need to put together a new system model that uses the ARM isa and is at least slightly extended from InOrderCPU.py/ Any other things to watch out for? Thanks - Eliot

On 7/4/2023 7:17 PM, Eliot Moss via gem5-users wrote: > Dear gem5-ers -- > > I am thinking of trying to put together something that roughly models ARM's > R82, which is an 8-stage, width 3, in order cpu. (It's also not a single > thing, but has numerous options you choose, and then set up RTL and can have > your design manufactured.) I see that there are three non-SMT and one SMT in > order pipeline models, but I'm not clear how I would use them -- swap them in > for the one that does not have 5, 9, or smt in its name? Or what? I do know > that I'll need to put together a new system model that uses the ARM isa and is > at least slightly extended from InOrderCPU.py/ Any other things to watch out > for? Thanks - Eliot Following up my own question a bit ... Is InOrderCPU (cpu/inorder) deprecated or something? Even adding InOrderCPU to CPU_MODELS in build_opts/ARM does not cause the inorder directory to compile. Not sure how to make it happen. Meanwhile, there is MinorCPU (cpu/minor), which seem perhaps intended to replace inorder. Is that right? Regards - Eliot