Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71999?usp=email )
Change subject: arch-riscv: Declear vecElemClass for RISC-V vector
extensions
......................................................................
arch-riscv: Declear vecElemClass for RISC-V vector extensions
Change-Id: I623a753499123d6934eda60ebcfe013c264cf458
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/vector.hh
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a4a792e..f60249a 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -244,7 +244,6 @@
{
/* Not applicable to RISCV */
-RegClass vecElemClass(VecElemClass, VecElemClassName, 0, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 0,
debug::IntRegs);
RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs);
diff --git a/src/arch/riscv/regs/vector.hh b/src/arch/riscv/regs/vector.hh
index d722c2d..05dd702 100644
--- a/src/arch/riscv/regs/vector.hh
+++ b/src/arch/riscv/regs/vector.hh
@@ -49,6 +49,7 @@
constexpr unsigned ELEN = 64;
constexpr unsigned VLEN = 256;
constexpr unsigned VLENB = VLEN / 8;
+constexpr unsigned NumVecElemPerVecReg = VLEN / ELEN;
using VecRegContainer = gem5::VecRegContainer<VLENB>;
using vreg_t = VecRegContainer;
@@ -68,12 +69,18 @@
// vector index
const int VecMemInternalReg0 = NumVecStandardRegs;
+static inline VecElemRegClassOps<uint64_t>
inline constexpr RegClass vecRegClass =
RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
ops(vecRegClassOps).
regType<VecRegContainer>();
+inline constexpr RegClass vecElemClass =
-
RegClass(VecElemClass, VecElemClassName, NumVecRegs *
NumVecElemPerVecReg,
-
debug::VecRegs).
-
ops(vecRegElemClassOps);
BitUnion32(VTYPE)
Bitfield<31> vill;
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I623a753499123d6934eda60ebcfe013c264cf458
Gerrit-Change-Number: 71999
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang rogerycchang@google.com
Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71999?usp=email )
Change subject: arch-riscv: Declear vecElemClass for RISC-V vector
extensions
......................................................................
arch-riscv: Declear vecElemClass for RISC-V vector extensions
Change-Id: I623a753499123d6934eda60ebcfe013c264cf458
---
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/vector.hh
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a4a792e..f60249a 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -244,7 +244,6 @@
{
/* Not applicable to RISCV */
-RegClass vecElemClass(VecElemClass, VecElemClassName, 0, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 0,
debug::IntRegs);
RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs);
diff --git a/src/arch/riscv/regs/vector.hh b/src/arch/riscv/regs/vector.hh
index d722c2d..05dd702 100644
--- a/src/arch/riscv/regs/vector.hh
+++ b/src/arch/riscv/regs/vector.hh
@@ -49,6 +49,7 @@
constexpr unsigned ELEN = 64;
constexpr unsigned VLEN = 256;
constexpr unsigned VLENB = VLEN / 8;
+constexpr unsigned NumVecElemPerVecReg = VLEN / ELEN;
using VecRegContainer = gem5::VecRegContainer<VLENB>;
using vreg_t = VecRegContainer;
@@ -68,12 +69,18 @@
// vector index
const int VecMemInternalReg0 = NumVecStandardRegs;
+static inline VecElemRegClassOps<uint64_t>
+ vecRegElemClassOps(NumVecElemPerVecReg);
static inline TypedRegClassOps<RiscvISA::VecRegContainer> vecRegClassOps;
inline constexpr RegClass vecRegClass =
RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
ops(vecRegClassOps).
regType<VecRegContainer>();
+inline constexpr RegClass vecElemClass =
+ RegClass(VecElemClass, VecElemClassName, NumVecRegs *
NumVecElemPerVecReg,
+ debug::VecRegs).
+ ops(vecRegElemClassOps);
BitUnion32(VTYPE)
Bitfield<31> vill;
--
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https://gem5-review.googlesource.com/c/public/gem5/+/71999?usp=email
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I623a753499123d6934eda60ebcfe013c264cf458
Gerrit-Change-Number: 71999
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycchang@google.com>