Roger Chang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email ) Change subject: arch-riscv: Add missing zbkb instructions ...................................................................... arch-riscv: Add missing zbkb instructions Add the following instructions: pack packh packw Change-Id: I74730c8132187d9a6eb8fc2389c2c28a8a9516df --- M src/arch/riscv/isa/decoder.isa 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 6f66c98..755be3d 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -1282,11 +1282,13 @@ } }}, IntDivOp); } - 0x4: decode RVTYPE { - 0x0: rv32_zext_h({{ - Rd = Rs1_uh; - }}); - } + 0x4: pack({{ + int xlen = rvSelect(32, 64); + Rd = rvSext( + (bits(Rs2, xlen/2-1, 0) << (xlen / 2)) | \ + bits(Rs1, xlen/2-1, 0) + ); + }}); 0x5: min({{ Rd_sd = std::min(rvSext(Rs1_sd), rvSext(Rs2_sd)); }}); @@ -1402,6 +1404,10 @@ } }}, IntDivOp); } + 0x4: packh({{ + // It doesn't need to sign ext as MSB is always 0 + Rd = (Rs2_ub << 8) | Rs1_ub; + }}); 0x5: maxu({{ Rd = rvSext(std::max(rvZext(Rs1), rvZext(Rs2))); }}); @@ -1459,8 +1465,8 @@ Rd_sd = Rs1_sw/Rs2_sw; } }}, IntDivOp); - 0x4: zext_h({{ - Rd = Rs1_uh; + 0x4: packw({{ + Rd_sd = sext<32>((Rs2_uh << 16) | Rs1_uh); }}); 0x10: sh2add_uw({{ Rd = (((uint64_t)Rs1_uw) << 2) + Rs2; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I74730c8132187d9a6eb8fc2389c2c28a8a9516df Gerrit-Change-Number: 70537 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Chang <rogerycchang@google.com>