Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-arm: Implement FEAT_TLBIOS ...................................................................... arch-arm: Implement FEAT_TLBIOS This feature is mandatory in Armv8.4 We are currently not distinguishing Inner and Outer domains. We therefore implement TLBIOS instructions as TLBIIS Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70567 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> --- M src/arch/arm/ArmSystem.py M src/arch/arm/insts/misc64.cc M src/arch/arm/regs/misc.cc M src/arch/arm/regs/misc.hh 4 files changed, 151 insertions(+), 1 deletion(-) Approvals: Richard Cooper: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 7367d80..9e2da8e 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -84,6 +84,7 @@ "FEAT_PAuth", # Armv8.4 "FEAT_SEL2", + "FEAT_TLBIOS", # Armv9.2 "FEAT_SME", # Optional in Armv9.2 # Others @@ -162,6 +163,7 @@ "FEAT_PAuth", # Armv8.4 "FEAT_SEL2", + "FEAT_TLBIOS", # Armv9.2 "FEAT_SME", ] @@ -192,7 +194,7 @@ class Armv84(Armv83): - extensions = Armv83.extensions + ["FEAT_SEL2"] + extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"] class Armv92(Armv84): diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 40a6ca4..c7423d9 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -241,6 +241,10 @@ } // AArch64 TLB Invalidate All, EL3, Inner Shareable case MISCREG_TLBI_ALLE3IS: + // AArch64 TLB Invalidate All, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE3OS: { TLBIALLEL tlbiOp(EL3, true); tlbiOp.broadcast(tc); @@ -258,6 +262,10 @@ } // AArch64 TLB Invalidate All, EL2, Inner Shareable case MISCREG_TLBI_ALLE2IS: + // AArch64 TLB Invalidate All, EL2, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE2OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -278,6 +286,10 @@ } // AArch64 TLB Invalidate All, EL1, Inner Shareable case MISCREG_TLBI_ALLE1IS: + // AArch64 TLB Invalidate All, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ALLE1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -313,6 +325,9 @@ return; } case MISCREG_TLBI_VMALLS12E1IS: + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VMALLS12E1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -322,6 +337,9 @@ return; } case MISCREG_TLBI_VMALLE1IS: + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VMALLE1OS: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -360,6 +378,10 @@ } // AArch64 TLB Invalidate by VA, EL3, Inner Shareable case MISCREG_TLBI_VAE3IS_Xt: + // AArch64 TLB Invalidate by VA, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAE3OS_Xt: { TLBIMVAA tlbiOp(EL3, true, static_cast<Addr>(bits(value, 43, 0)) << 12, @@ -370,6 +392,10 @@ } // AArch64 TLB Invalidate by VA, Last Level, EL3, Inner Shareable case MISCREG_TLBI_VALE3IS_Xt: + // AArch64 TLB Invalidate by VA, Last Level, EL3, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VALE3OS_Xt: { TLBIMVAA tlbiOp(EL3, true, static_cast<Addr>(bits(value, 43, 0)) << 12, @@ -430,6 +456,10 @@ } // AArch64 TLB Invalidate by VA, EL2, Inner Shareable case MISCREG_TLBI_VAE2IS_Xt: + // AArch64 TLB Invalidate by VA, EL2, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAE2OS_Xt: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); @@ -455,6 +485,10 @@ } // AArch64 TLB Invalidate by VA, Last Level, EL2, Inner Shareable case MISCREG_TLBI_VALE2IS_Xt: + // AArch64 TLB Invalidate by VA, Last Level, EL2, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VALE2OS_Xt: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); @@ -526,6 +560,10 @@ } // AArch64 TLB Invalidate by VA, EL1, Inner Shareable case MISCREG_TLBI_VAE1IS_Xt: + // AArch64 TLB Invalidate by VA, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAE1OS_Xt: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : @@ -591,6 +629,10 @@ } // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable case MISCREG_TLBI_ASIDE1IS_Xt: + // AArch64 TLB Invalidate by ASID, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_ASIDE1OS_Xt: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); auto asid = asid_16bits ? bits(value, 63, 48) : @@ -653,6 +695,10 @@ } // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable case MISCREG_TLBI_VAAE1IS_Xt: + // AArch64 TLB Invalidate by VA, All ASID, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAAE1OS_Xt: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -675,6 +721,11 @@ // AArch64 TLB Invalidate by VA, All ASID, // Last Level, EL1, Inner Shareable case MISCREG_TLBI_VAALE1IS_Xt: + // AArch64 TLB Invalidate by VA, All ASID, + // Last Level, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_VAALE1OS_Xt: { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -735,6 +786,11 @@ // AArch64 TLB Invalidate by Intermediate Physical Address, // Stage 2, EL1, Inner Shareable case MISCREG_TLBI_IPAS2E1IS_Xt: + // AArch64 TLB Invalidate by Intermediate Physical Address, + // Stage 2, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_IPAS2E1OS_Xt: { if (EL2Enabled(tc)) { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); @@ -755,6 +811,11 @@ // AArch64 TLB Invalidate by Intermediate Physical Address, // Stage 2, Last Level, EL1, Inner Shareable case MISCREG_TLBI_IPAS2LE1IS_Xt: + // AArch64 TLB Invalidate by Intermediate Physical Address, + // Stage 2, Last Level, EL1, Outer Shareable + // We are currently not distinguishing Inner and Outer domains. + // We therefore implement TLBIOS instructions as TLBIIS + case MISCREG_TLBI_IPAS2LE1OS_Xt: { if (EL2Enabled(tc)) { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 2d76143..ec5670e 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -753,6 +753,12 @@ { MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt }, { MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt }, { MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt }, + { MiscRegNum64(1, 0, 8, 1, 0), MISCREG_TLBI_VMALLE1OS }, + { MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS_Xt }, + { MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS_Xt }, + { MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS_Xt }, + { MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS_Xt }, + { MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS_Xt }, { MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS }, { MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt }, { MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt }, @@ -778,12 +784,19 @@ { MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt }, { MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt }, { MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt }, + { MiscRegNum64(1, 4, 8, 1, 0), MISCREG_TLBI_ALLE2OS }, + { MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS_Xt }, + { MiscRegNum64(1, 4, 8, 1, 4), MISCREG_TLBI_ALLE1OS }, + { MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS_Xt }, + { MiscRegNum64(1, 4, 8, 1, 6), MISCREG_TLBI_VMALLS12E1OS }, { MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS }, { MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt }, { MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS }, { MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt }, { MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS }, + { MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS_Xt }, { MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt }, + { MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS_Xt }, { MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt }, { MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 }, { MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt }, @@ -792,6 +805,9 @@ { MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 }, { MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt }, { MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt }, + { MiscRegNum64(1, 6, 8, 1, 0), MISCREG_TLBI_ALLE3OS }, + { MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS_Xt }, + { MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS_Xt }, { MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS }, { MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt }, { MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt }, @@ -3874,6 +3890,7 @@ isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0; isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0; isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0; + isar0_el1.tlb = release->has(ArmExtension::FEAT_TLBIOS) ? 0x1 : 0x0; return isar0_el1; }()) .faultRead(EL1, HCR_TRAP(tid3)) @@ -4339,6 +4356,24 @@ .monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_AT_S1E3W_Xt) .monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_VMALLE1OS) + .faultWrite(EL1, HCR_TRAP(ttlb)) + .writes(1).exceptUserMode(); + InitReg(MISCREG_TLBI_VAE1OS_Xt) + .faultWrite(EL1, HCR_TRAP(ttlb)) + .writes(1).exceptUserMode(); + InitReg(MISCREG_TLBI_ASIDE1OS_Xt) + .faultWrite(EL1, HCR_TRAP(ttlb)) + .writes(1).exceptUserMode(); + InitReg(MISCREG_TLBI_VAAE1OS_Xt) + .faultWrite(EL1, HCR_TRAP(ttlb)) + .writes(1).exceptUserMode(); + InitReg(MISCREG_TLBI_VALE1OS_Xt) + .faultWrite(EL1, HCR_TRAP(ttlb)) + .writes(1).exceptUserMode(); + InitReg(MISCREG_TLBI_VAALE1OS_Xt) + .faultWrite(EL1, HCR_TRAP(ttlb)) + .writes(1).exceptUserMode(); InitReg(MISCREG_TLBI_VMALLE1IS) .faultWrite(EL1, HCR_TRAP(ttlb)) .writes(1).exceptUserMode(); @@ -4375,6 +4410,20 @@ InitReg(MISCREG_TLBI_VAALE1_Xt) .faultWrite(EL1, HCR_TRAP(ttlb)) .writes(1).exceptUserMode(); + InitReg(MISCREG_TLBI_IPAS2E1OS_Xt) + .hypWrite().monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_IPAS2LE1OS_Xt) + .hypWrite().monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_ALLE2OS) + .monNonSecureWrite().hypWrite(); + InitReg(MISCREG_TLBI_VAE2OS_Xt) + .monNonSecureWrite().hypWrite(); + InitReg(MISCREG_TLBI_ALLE1OS) + .hypWrite().monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_VALE2OS_Xt) + .monNonSecureWrite().hypWrite(); + InitReg(MISCREG_TLBI_VMALLS12E1OS) + .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) @@ -4403,6 +4452,12 @@ .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBI_VMALLS12E1) .hypWrite().monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_ALLE3OS) + .monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_VAE3OS_Xt) + .monSecureWrite().monNonSecureWrite(); + InitReg(MISCREG_TLBI_VALE3OS_Xt) + .monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_ALLE3IS) .monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_VAE3IS_Xt) diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index abbd1c6..c43cf74 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -681,11 +681,17 @@ MISCREG_AT_S1E3R_Xt, MISCREG_AT_S1E3W_Xt, MISCREG_TLBI_VMALLE1IS, + MISCREG_TLBI_VMALLE1OS, MISCREG_TLBI_VAE1IS_Xt, + MISCREG_TLBI_VAE1OS_Xt, MISCREG_TLBI_ASIDE1IS_Xt, + MISCREG_TLBI_ASIDE1OS_Xt, MISCREG_TLBI_VAAE1IS_Xt, + MISCREG_TLBI_VAAE1OS_Xt, MISCREG_TLBI_VALE1IS_Xt, + MISCREG_TLBI_VALE1OS_Xt, MISCREG_TLBI_VAALE1IS_Xt, + MISCREG_TLBI_VAALE1OS_Xt, MISCREG_TLBI_VMALLE1, MISCREG_TLBI_VAE1_Xt, MISCREG_TLBI_ASIDE1_Xt, @@ -693,12 +699,19 @@ MISCREG_TLBI_VALE1_Xt, MISCREG_TLBI_VAALE1_Xt, MISCREG_TLBI_IPAS2E1IS_Xt, + MISCREG_TLBI_IPAS2E1OS_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, + MISCREG_TLBI_IPAS2LE1OS_Xt, MISCREG_TLBI_ALLE2IS, + MISCREG_TLBI_ALLE2OS, MISCREG_TLBI_VAE2IS_Xt, + MISCREG_TLBI_VAE2OS_Xt, MISCREG_TLBI_ALLE1IS, + MISCREG_TLBI_ALLE1OS, MISCREG_TLBI_VALE2IS_Xt, + MISCREG_TLBI_VALE2OS_Xt, MISCREG_TLBI_VMALLS12E1IS, + MISCREG_TLBI_VMALLS12E1OS, MISCREG_TLBI_IPAS2E1_Xt, MISCREG_TLBI_IPAS2LE1_Xt, MISCREG_TLBI_ALLE2, @@ -707,8 +720,11 @@ MISCREG_TLBI_VALE2_Xt, MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_ALLE3IS, + MISCREG_TLBI_ALLE3OS, MISCREG_TLBI_VAE3IS_Xt, + MISCREG_TLBI_VAE3OS_Xt, MISCREG_TLBI_VALE3IS_Xt, + MISCREG_TLBI_VALE3OS_Xt, MISCREG_TLBI_ALLE3, MISCREG_TLBI_VAE3_Xt, MISCREG_TLBI_VALE3_Xt, @@ -2344,11 +2360,17 @@ "at_s1e3r_xt", "at_s1e3w_xt", "tlbi_vmalle1is", + "tlbi_vmalle1os", "tlbi_vae1is_xt", + "tlbi_vae1os_xt", "tlbi_aside1is_xt", + "tlbi_aside1os_xt", "tlbi_vaae1is_xt", + "tlbi_vaae1os_xt", "tlbi_vale1is_xt", + "tlbi_vale1os_xt", "tlbi_vaale1is_xt", + "tlbi_vaale1os_xt", "tlbi_vmalle1", "tlbi_vae1_xt", "tlbi_aside1_xt", @@ -2356,12 +2378,19 @@ "tlbi_vale1_xt", "tlbi_vaale1_xt", "tlbi_ipas2e1is_xt", + "tlbi_ipas2e1os_xt", "tlbi_ipas2le1is_xt", + "tlbi_ipas2le1os_xt", "tlbi_alle2is", + "tlbi_alle2os", "tlbi_vae2is_xt", + "tlbi_vae2os_xt", "tlbi_alle1is", + "tlbi_alle1os", "tlbi_vale2is_xt", + "tlbi_vale2os_xt", "tlbi_vmalls12e1is", + "tlbi_vmalls12e1os", "tlbi_ipas2e1_xt", "tlbi_ipas2le1_xt", "tlbi_alle2", @@ -2370,8 +2399,11 @@ "tlbi_vale2_xt", "tlbi_vmalls12e1", "tlbi_alle3is", + "tlbi_alle3os", "tlbi_vae3is_xt", + "tlbi_vae3os_xt", "tlbi_vale3is_xt", + "tlbi_vale3os_xt", "tlbi_alle3", "tlbi_vae3_xt", "tlbi_vale3_xt", -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3 Gerrit-Change-Number: 70567 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Andreas Sandberg <andreas.sandberg@arm.com> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <power.jg@gmail.com> Gerrit-Reviewer: Richard Cooper <richard.cooper@arm.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com>