ExceptionLevel el = (ExceptionLevel) currEL(tc);

  assert(count == activityCount);

          if (req->isLLSC()) {

  if (dmaTransferEvent.scheduled()) {
      reschedule = dmaTransferEvent.when();
      event = Transfer;

  SERIALIZE_SCALAR(reschedule);
  SERIALIZE_ENUM(event);

Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/70297?usp=email ) Change subject: misc: Fix 'unused variable' clang errors with gem5.fast ...................................................................... misc: Fix 'unused variable' clang errors with gem5.fast Change-Id: I2bb8ac10e8db69fa82abe41577cd8e5db575e93d --- M src/arch/arm/self_debug.cc M src/arch/sparc/faults.cc M src/cpu/activity.cc M src/cpu/minor/execute.cc M src/cpu/simple/atomic.cc M src/dev/storage/ide_disk.cc M src/mem/ruby/system/Sequencer.cc 7 files changed, 30 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc index a4e685f..a99cf0a 100644 --- a/src/arch/arm/self_debug.cc +++ b/src/arch/arm/self_debug.cc @@ -127,9 +127,7 @@ return NoFault; ExceptionLevel el = (ExceptionLevel) currEL(tc); - int idxtmp = -1; for (auto &p: arWatchPoints){ - idxtmp ++; if (p.enable) { if (p.test(tc, vaddr, el, write, atomic, size)) { return triggerWatchpointException(tc, vaddr, write, cm); diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index ff80ec1..d3d5ae4 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -302,7 +302,6 @@ void doREDFault(ThreadContext *tc, TrapType tt) { - RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL); RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); @@ -313,8 +312,6 @@ RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL); auto &pc = tc->pcState().as<PCState>(); - TL++; - Addr pcMask = pstate.am ? mask(32) : mask(64); // set TSTATE.gl to gl diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc index f10b1ce..cae5932 100644 --- a/src/cpu/activity.cc +++ b/src/cpu/activity.cc @@ -151,6 +151,7 @@ void ActivityRecorder::validate() { +#ifdef DEBUG int count = 0; for (int i = 0; i <= longestLatency; ++i) { if (activityBuffer[-i]) { @@ -165,6 +166,7 @@ } assert(count == activityCount); +#endif } } // namespace gem5 diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index 5eaaf58..5f5b3ac 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -568,10 +568,6 @@ /* Number of memory ops issues this cycle to check for memoryIssueLimit */ unsigned num_mem_insts_issued = 0; - /* Number of instructions discarded this cycle in order to enforce a - * discardLimit. @todo, add that parameter? */ - unsigned num_insts_discarded = 0; - do { MinorDynInstPtr inst = insts_in->insts[thread.inputIndex]; Fault fault = inst->fault; @@ -800,9 +796,7 @@ if (issued_mem_ref) num_mem_insts_issued++; - if (discarded) { - num_insts_discarded++; - } else if (!inst->isBubble()) { + if (!discarded && !inst->isBubble()) { num_insts_issued++; if (num_insts_issued == issueLimit) diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 5c9fc29..d8e4883 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -462,7 +462,9 @@ Addr frag_addr = addr; int frag_size = 0; int size_left = size; +#ifdef DEBUG int curr_frag_id = 0; +#endif bool predicate; Fault fault = NoFault; @@ -480,11 +482,15 @@ bool do_access = true; // flag to suppress cache access if (req->isLLSC()) { +#ifdef DEBUG assert(curr_frag_id == 0); +#endif do_access = thread->getIsaPtr()->handleLockedWrite(req, dcachePort.cacheBlockMask); } else if (req->isSwap()) { +#ifdef DEBUG assert(curr_frag_id == 0); +#endif if (req->isCondSwap()) { assert(res); req->setExtraData(*res); @@ -508,7 +514,9 @@ panic_if(pkt.isError(), "Data write (%s) failed: %s", pkt.getAddrRange().to_string(), pkt.print()); if (req->isSwap()) { +#ifdef DEBUG assert(res && curr_frag_id == 0); +#endif memcpy(res, pkt.getConstPtr<uint8_t>(), size); } } @@ -538,7 +546,9 @@ //Move the pointer we're reading into to the correct location. data += frag_size; +#ifdef DEBUG curr_frag_id++; +#endif } } diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc index e43437f..89c2753 100644 --- a/src/dev/storage/ide_disk.cc +++ b/src/dev/storage/ide_disk.cc @@ -1072,40 +1072,56 @@ Tick reschedule = 0; Events_t event = None; +#ifdef DEBUG int eventCount = 0; +#endif if (dmaTransferEvent.scheduled()) { reschedule = dmaTransferEvent.when(); event = Transfer; +#ifdef DEBUG eventCount++; +#endif } if (dmaReadWaitEvent.scheduled()) { reschedule = dmaReadWaitEvent.when(); event = ReadWait; +#ifdef DEBUG eventCount++; +#endif } if (dmaWriteWaitEvent.scheduled()) { reschedule = dmaWriteWaitEvent.when(); event = WriteWait; +#ifdef DEBUG eventCount++; +#endif } if (dmaPrdReadEvent.scheduled()) { reschedule = dmaPrdReadEvent.when(); event = PrdRead; +#ifdef DEBUG eventCount++; +#endif } if (dmaReadEvent.scheduled()) { reschedule = dmaReadEvent.when(); event = DmaRead; +#ifdef DEBUG eventCount++; +#endif } if (dmaWriteEvent.scheduled()) { reschedule = dmaWriteEvent.when(); event = DmaWrite; +#ifdef DEBUG eventCount++; +#endif } +#ifdef DEBUG assert(eventCount <= 1); +#endif SERIALIZE_SCALAR(reschedule); SERIALIZE_ENUM(event); diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 24439d6..3b75619 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -464,8 +464,6 @@ // ruby request was outstanding. Since only 1 ruby request was made, // profile the ruby latency once. bool ruby_request = true; - int aliased_stores = 0; - int aliased_loads = 0; while (!seq_req_list.empty()) { SequencerRequest &seq_req = seq_req_list.front(); @@ -520,9 +518,8 @@ recordMissLatency(&seq_req, success, mach, externalHit, initialRequestTime, forwardRequestTime, firstResponseTime); - } else { - aliased_stores++; } + markRemoved(); hitCallback(&seq_req, data, success, mach, externalHit, initialRequestTime, forwardRequestTime, @@ -532,7 +529,6 @@ // handle read request assert(!ruby_request); markRemoved(); - aliased_loads++; hitCallback(&seq_req, data, true, mach, externalHit, initialRequestTime, forwardRequestTime, firstResponseTime, !ruby_request); @@ -565,15 +561,12 @@ // ruby request was outstanding. Since only 1 ruby request was made, // profile the ruby latency once. bool ruby_request = true; - int aliased_loads = 0; while (!seq_req_list.empty()) { SequencerRequest &seq_req = seq_req_list.front(); if (ruby_request) { assert((seq_req.m_type == RubyRequestType_LD) || (seq_req.m_type == RubyRequestType_Load_Linked) || (seq_req.m_type == RubyRequestType_IFETCH)); - } else { - aliased_loads++; } if ((seq_req.m_type != RubyRequestType_LD) && (seq_req.m_type != RubyRequestType_Load_Linked) && -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/70297?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2bb8ac10e8db69fa82abe41577cd8e5db575e93d Gerrit-Change-Number: 70297 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce <bbruce@ucdavis.edu>