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My New Instruction in RISCV Does Not Add Instructions It Depends on

TI
Thierry ishimwe
Fri, Nov 3, 2023 7:57 PM

Hi,I've created a new instruction in the RISC-V ISA with U-type properties,
which I've named "test"(see assembly below). Unlike other U-type
instructions, this instruction uses a source register rather than having a
destination register. Its main purpose is to provide information to the
processor without returning any results.while debugging, I observed that
the "test" instruction, which is supposed to depend on the "addi"
instruction above it, gets issued before the "addi" instruction's results
have completed or broadcasted. Additionally, when the "addi" instruction is
waking up its dependents, it incorrectly reports having zero dependents
instead of the expected one dependent, which is the "test" instruction. I
also checked the "test" instruction during the dispatch phase and found
that its source register is marked as ready.I suspect that the issue may be
related to how I integrated this new instruction into gem5. Since it's a
unique instruction with properties similar to U-types, I modified the
standard.isa(see below) file for RISC-V. In this modification, I copied the
U-type instruction template and made a single change(I replaced 'regs =
['srcDstIdx(0)']' with 'regs = ['srcRegIdx(0)'). I have not provided any
content in the "decoder.isa" file since my "test" instruction does not
return any values.Am I doing this right?asm example

  • 1085e: 28 08        addi a0, sp, 24
    10860: 2b 85 00 00  test a0, 8
    10864: e2 66        ld     a3, 24(sp)*

test instruction U-type template (standard.isa)

*def format TestUOp(code, opt_flags) {{
regs = ['srcRegIdx(0)']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': 'imm = IMM20;',
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ImmExecute.subst(iop)
}};

Hi,I've created a new instruction in the RISC-V ISA with U-type properties, which I've named "*test*"(see assembly below). Unlike other U-type instructions, this instruction uses a source register rather than having a destination register. Its main purpose is to provide information to the processor without returning any results.while debugging, I observed that the "*test*" instruction, which is supposed to depend on the "addi" instruction above it, gets issued before the "addi" instruction's results have completed or broadcasted. Additionally, when the "addi" instruction is waking up its dependents, it incorrectly reports having zero dependents instead of the expected one dependent, which is the "*test*" instruction. I also checked the "*test*" instruction during the dispatch phase and found that its source register is marked as ready.I suspect that the issue may be related to how I integrated this new instruction into gem5. Since it's a unique instruction with properties similar to U-types, I modified the standard.isa(see below) file for RISC-V. In this modification, I copied the U-type instruction template and made a single change(I replaced 'regs = ['srcDstIdx(0)']' with 'regs = ['srcRegIdx(0)'). I have not provided any content in the "decoder.isa" file since my "test" instruction does not return any values.Am I doing this right?asm example * 1085e: 28 08 addi a0, sp, 24 10860: 2b 85 00 00 test a0, 8 10864: e2 66 ld a3, 24(sp)* test instruction U-type template (standard.isa) *def format TestUOp(code, *opt_flags) {{ regs = ['srcRegIdx(0)'] iop = InstObjParams(name, Name, 'ImmOp<int64_t>', {'code': code, 'imm_code': 'imm = IMM20;', 'regs': ','.join(regs)}, opt_flags) header_output = ImmDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) decode_block = BasicDecode.subst(iop) exec_output = ImmExecute.subst(iop) }};*