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[S] Change in gem5/gem5[develop]: stdlib: Fix formatting of DRAMSys component names

BB
Bobby Bruce (Gerrit)
Wed, Mar 22, 2023 7:22 PM

Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69199?usp=email )

Change subject: stdlib: Fix formatting of DRAMSys component names
......................................................................

stdlib: Fix formatting of DRAMSys component names

This keeps the DRAMSys component names in-keeping with the formatting of
the other memory components.

Change-Id: I7f9d9c5292745115c776fd3eafca99520b8b1c15

M configs/example/gem5_library/dramsys/arm-hello-dramsys.py
M src/python/gem5/components/memory/init.py
M src/python/gem5/components/memory/dramsys.py
3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py
b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py
index 62a55e3..8b25a36 100644
--- a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py
+++ b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py
@@ -36,7 +36,7 @@
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
-from gem5.components.memory import DRAMSys_DDR3_1600
+from gem5.components.memory import DRAMSysDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy
import (
@@ -53,7 +53,7 @@
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32kB", l1i_size="32kB")

We use a single channel DDR3_1600 memory system

-memory = DRAMSys_DDR3_1600(recordable=True)
+memory = DRAMSysDDR3_1600(recordable=True)

We use a simple Timing processor with one core.

processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM,
num_cores=1)
diff --git a/src/python/gem5/components/memory/init.py
b/src/python/gem5/components/memory/init.py
index 9f13157..8a7b5ef 100644
--- a/src/python/gem5/components/memory/init.py
+++ b/src/python/gem5/components/memory/init.py
@@ -37,10 +37,10 @@

try:
from .dramsys import DRAMSysMem

  • from .dramsys import DRAMSys_DDR4_1866
  • from .dramsys import DRAMSys_DDR3_1600
  • from .dramsys import DRAMSys_LPDDR4_3200
  • from .dramsys import DRAMSys_HBM2
  • from .dramsys import DRAMSysDDR4_1866
  • from .dramsys import DRAMSysDDR3_1600
  • from .dramsys import DRAMSysLPDDR4_3200
  • from .dramsys import DRAMSysHBM2
    except:

    In the case that DRAMSys is not compiled into the gem5 binary,

importing
# DRAMSys components will fail. This try-exception statement is needed
to
diff --git a/src/python/gem5/components/memory/dramsys.py
b/src/python/gem5/components/memory/dramsys.py
index 887a8da..28f3bd3 100644
--- a/src/python/gem5/components/memory/dramsys.py
+++ b/src/python/gem5/components/memory/dramsys.py
@@ -96,7 +96,7 @@
self.bridge.addr_ranges = ranges[0]

-class DRAMSys_DDR4_1866(DRAMSysMem):
+class DRAMSysDDR4_1866(DRAMSysMem):
def init(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of
DRAMSys is enabled.
@@ -110,7 +110,7 @@
)

-class DRAMSys_DDR3_1600(DRAMSysMem):
+class DRAMSysDDR3_1600(DRAMSysMem):
def init(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of
DRAMSys is enabled.
@@ -124,7 +124,7 @@
)

-class DRAMSys_LPDDR4_3200(DRAMSysMem):
+class DRAMSysLPDDR4_3200(DRAMSysMem):
def init(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of
DRAMSys is enabled.
@@ -138,7 +138,7 @@
)

-class DRAMSys_HBM2(DRAMSysMem):
+class DRAMSysHBM2(DRAMSysMem):
def init(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of
DRAMSys is enabled.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7f9d9c5292745115c776fd3eafca99520b8b1c15
Gerrit-Change-Number: 69199
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce bbruce@ucdavis.edu
Gerrit-MessageType: newchange

Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69199?usp=email ) Change subject: stdlib: Fix formatting of DRAMSys component names ...................................................................... stdlib: Fix formatting of DRAMSys component names This keeps the DRAMSys component names in-keeping with the formatting of the other memory components. Change-Id: I7f9d9c5292745115c776fd3eafca99520b8b1c15 --- M configs/example/gem5_library/dramsys/arm-hello-dramsys.py M src/python/gem5/components/memory/__init__.py M src/python/gem5/components/memory/dramsys.py 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py index 62a55e3..8b25a36 100644 --- a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py +++ b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py @@ -36,7 +36,7 @@ from gem5.isas import ISA from gem5.utils.requires import requires from gem5.resources.resource import Resource -from gem5.components.memory import DRAMSys_DDR3_1600 +from gem5.components.memory import DRAMSysDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import ( @@ -53,7 +53,7 @@ cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32kB", l1i_size="32kB") # We use a single channel DDR3_1600 memory system -memory = DRAMSys_DDR3_1600(recordable=True) +memory = DRAMSysDDR3_1600(recordable=True) # We use a simple Timing processor with one core. processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1) diff --git a/src/python/gem5/components/memory/__init__.py b/src/python/gem5/components/memory/__init__.py index 9f13157..8a7b5ef 100644 --- a/src/python/gem5/components/memory/__init__.py +++ b/src/python/gem5/components/memory/__init__.py @@ -37,10 +37,10 @@ try: from .dramsys import DRAMSysMem - from .dramsys import DRAMSys_DDR4_1866 - from .dramsys import DRAMSys_DDR3_1600 - from .dramsys import DRAMSys_LPDDR4_3200 - from .dramsys import DRAMSys_HBM2 + from .dramsys import DRAMSysDDR4_1866 + from .dramsys import DRAMSysDDR3_1600 + from .dramsys import DRAMSysLPDDR4_3200 + from .dramsys import DRAMSysHBM2 except: # In the case that DRAMSys is not compiled into the gem5 binary, importing # DRAMSys components will fail. This try-exception statement is needed to diff --git a/src/python/gem5/components/memory/dramsys.py b/src/python/gem5/components/memory/dramsys.py index 887a8da..28f3bd3 100644 --- a/src/python/gem5/components/memory/dramsys.py +++ b/src/python/gem5/components/memory/dramsys.py @@ -96,7 +96,7 @@ self.bridge.addr_ranges = ranges[0] -class DRAMSys_DDR4_1866(DRAMSysMem): +class DRAMSysDDR4_1866(DRAMSysMem): def __init__(self, recordable: bool): """ :param recordable: Whether the database recording feature of DRAMSys is enabled. @@ -110,7 +110,7 @@ ) -class DRAMSys_DDR3_1600(DRAMSysMem): +class DRAMSysDDR3_1600(DRAMSysMem): def __init__(self, recordable: bool): """ :param recordable: Whether the database recording feature of DRAMSys is enabled. @@ -124,7 +124,7 @@ ) -class DRAMSys_LPDDR4_3200(DRAMSysMem): +class DRAMSysLPDDR4_3200(DRAMSysMem): def __init__(self, recordable: bool): """ :param recordable: Whether the database recording feature of DRAMSys is enabled. @@ -138,7 +138,7 @@ ) -class DRAMSys_HBM2(DRAMSysMem): +class DRAMSysHBM2(DRAMSysMem): def __init__(self, recordable: bool): """ :param recordable: Whether the database recording feature of DRAMSys is enabled. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/69199?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7f9d9c5292745115c776fd3eafca99520b8b1c15 Gerrit-Change-Number: 69199 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-MessageType: newchange